| Apollo Register Documentation v2.2.0

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IOMSTR - I2C/SPI Master

### IOMSTR Register Index

0x00000000: | FIFO - FIFO Access Port
0x00000100: | FIFOPTR - Current FIFO Pointers
0x00000104: | TLNGTH - Transfer Length
0x00000108: | FIFOTHR - FIFO Threshold Configuration
0x0000010C: | CLKCFG - I/O Clock Configuration
0x00000110: | CMD - Command Register
0x00000114: | CMDRPT - Command Repeat Register
0x00000118: | STATUS - Status Register
0x0000011C: | CFG - I/O Master Configuration
0x00000200: | INTEN - IO Master Interrupts: Enable
0x00000204: | INTSTAT - IO Master Interrupts: Status
0x00000208: | INTCLR - IO Master Interrupts: Clear
0x0000020C: | INTSET - IO Master Interrupts: Set

### FIFO - FIFO Access Port

### Address:

Instance 0 Address: | 0x50004000
Instance 1 Address: | 0x50005000

### Description:

FIFO Access Port

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
FIFO 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | FIFO | RW | FIFO access port.

### FIFOPTR - Current FIFO Pointers

### Address:

Instance 0 Address: | 0x50004100
Instance 1 Address: | 0x50005100

### Description:

Current FIFO Pointers

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | FIFOREM 0x0 | RSVD 0x0 | FIFOSIZ 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:23 | RSVD | RO | RESERVED
22:16 | FIFOREM | RO | The number of bytes remaining in the FIFO (i.e. 64-FIFOSIZ).
15:7 | RSVD | RO | RESERVED
6:0 | FIFOSIZ | RO | The number of bytes currently in the FIFO.

### TLNGTH - Transfer Length

### Address:

Instance 0 Address: | 0x50004104
Instance 1 Address: | 0x50005104

### Description:

Transfer Length

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | TLNGTH 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:12 | RSVD | RO | RESERVED
11:0 | TLNGTH | RO | Remaining transfer length.

### FIFOTHR - FIFO Threshold Configuration

### Address:

Instance 0 Address: | 0x50004108
Instance 1 Address: | 0x50005108

### Description:

FIFO Threshold Configuration

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | FIFOWTHR 0x0 | RSVD 0x0 | FIFORTHR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:14 | RSVD | RO | RESERVED
13:8 | FIFOWTHR | RW | FIFO write threshold.
7:6 | RSVD | RO | RESERVED
5:0 | FIFORTHR | RW | FIFO read threshold.

### CLKCFG - I/O Clock Configuration

### Address:

Instance 0 Address: | 0x5000410C
Instance 1 Address: | 0x5000510C

### Description:

I/O Clock Configuration

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
TOTPER 0x0 | LOWPER 0x0 | RSVD 0x0 | DIVEN 0x0 | DIV3 0x0 | FSEL 0x0 | RSVD 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:24 | TOTPER | RW | Clock total count minus 1.
23:16 | LOWPER | RW | Clock low count minus 1.
15:13 | RSVD | RO | RESERVED
12 | DIVEN | RW | Enable clock division by TOTPER. DIS = 0x0 - Disable TOTPER division. EN = 0x1 - Enable TOTPER division.
11 | DIV3 | RW | Enable divide by 3. DIS = 0x0 - Select divide by 1. EN = 0x1 - Select divide by 3.
10:8 | FSEL | RW | Select the input clock frequency. HFRC_DIV64 = 0x0 - Selects the HFRC / 64 as the input clock. HFRC = 0x1 - Selects the HFRC as the input clock. HFRC_DIV2 = 0x2 - Selects the HFRC / 2 as the input clock. HFRC_DIV4 = 0x3 - Selects the HFRC / 4 as the input clock. HFRC_DIV8 = 0x4 - Selects the HFRC / 8 as the input clock. HFRC_DIV16 = 0x5 - Selects the HFRC / 16 as the input clock. HFRC_DIV32 = 0x6 - Selects the HFRC / 32 as the input clock. RSVD = 0x7 - Reserved.
7:0 | RSVD | RO | RESERVED

### CMD - Command Register

### Address:

Instance 0 Address: | 0x50004110
Instance 1 Address: | 0x50005110

### Description:

Command Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMD 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | CMD | RW | This register is the I/O Command. POS_LENGTH = 0x0 - LSB bit position of the CMD LENGTH field. POS_OFFSET = 0x8 - LSB bit position of the CMD OFFSET field. POS_ADDRESS = 0x16 - LSB bit position of the I2C CMD ADDRESS field. POS_CHNL = 0x16 - LSB bit position of the SPI CMD CHANNEL field. POS_UPLNGTH = 0x23 - LSB bit position of the SPI CMD UPLNGTH field. POS_10BIT = 0x26 - LSB bit position of the I2C CMD 10-bit field. POS_LSB = 0x27 - LSB bit position of the CMD LSB-first field. POS_CONT = 0x28 - LSB bit position of the CMD CONTinue field. POS_OPER = 0x29 - LSB bit position of the CMD OPERation field. MSK_LENGTH = 0xFF - LSB bit mask of the CMD LENGTH field. MSK_OFFSET = 0xFF00 - LSB bit mask of the CMD OFFSET field. MSK_ADDRESS = 0xFF0000 - LSB bit mask of the I2C CMD ADDRESS field. MSK_CHNL = 0x70000 - LSB bit mask of the SPI CMD CHANNEL field. MSK_UPLNGTH = 0x7800000 - LSB bit mask of the SPI CMD UPLNGTH field. MSK_10BIT = 0x4000000 - LSB bit mask of the I2C CMD 10-bit field. MSK_LSB = 0x8000000 - LSB bit mask of the CMD LSB-first field. MSK_CONT = 0x10000000 - LSB bit mask of the CMD CONTinue field. MSK_OPER = 0xE0000000 - LSB bit mask of the CMD OPERation field.

### CMDRPT - Command Repeat Register

### Address:

Instance 0 Address: | 0x50004114
Instance 1 Address: | 0x50005114

### Description:

Command Repeat Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CMDRPT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:5 | RSVD | RO | RESERVED
4:0 | CMDRPT | RW | These bits hold the Command repeat count.

### STATUS - Status Register

### Address:

Instance 0 Address: | 0x50004118
Instance 1 Address: | 0x50005118

### Description:

Status Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | IDLEST 0x0 | CMDACT 0x0 | ERR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED
2 | IDLEST | RO | This bit indicates if the I/O state machine is IDLE. IDLE = 0x1 - The I/O state machine is in the idle state.
1 | CMDACT | RO | This bit indicates if the I/O Command is active. ACTIVE = 0x1 - An I/O command is active.
0 | ERR | RO | This bit indicates if an error interrupt has occurred. ERROR = 0x1 - An error has been indicated by the IOM.

### CFG - I/O Master Configuration

### Address:

Instance 0 Address: | 0x5000411C
Instance 1 Address: | 0x5000511C

### Description:

I/O Master Configuration

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
IFCEN 0x0 | RSVD 0x0 | SPHA 0x0 | SPOL 0x0 | IFCSEL 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | IFCEN | RW | This bit enables the IO Master. DIS = 0x0 - Disable the IO Master. EN = 0x1 - Enable the IO Master.
30:3 | RSVD | RO | RESERVED
2 | SPHA | RW | This bit selects SPI phase. SAMPLE_LEADING_EDGE = 0x0 - Sample on the leading (first) clock edge. SAMPLE_TRAILING_EDGE = 0x1 - Sample on the trailing (second) clock edge.
1 | SPOL | RW | This bit selects SPI polarity. CLK_BASE_0 = 0x0 - The base value of the clock is 0. CLK_BASE_1 = 0x1 - The base value of the clock is 1.
0 | IFCSEL | RW | This bit selects the I/O interface. I2C = 0x0 - Selects I2C interface for the I/O Master. SPI = 0x1 - Selects SPI interface for the I/O Master.

### INTEN - IO Master Interrupts: Enable

### Address:

Instance 0 Address: | 0x50004200
Instance 1 Address: | 0x50005200

### Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ARB 0x0 | STOP 0x0 | START 0x0 | ICMD 0x0 | IACC 0x0 | WTLEN 0x0 | NAK 0x0 | FOVFL 0x0 | FUNDFL 0x0 | THR 0x0 | CMDCMP 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED
10 | ARB | RW | This is the arbitration loss interrupt.
9 | STOP | RW | This is the STOP command interrupt.
8 | START | RW | This is the START command interrupt.
7 | ICMD | RW | This is the illegal command interrupt.
6 | IACC | RW | This is the illegal FIFO access interrupt.
5 | WTLEN | RW | This is the write length mismatch interrupt.
4 | NAK | RW | This is the I2C NAK interrupt.
3 | FOVFL | RW | This is the Read FIFO Overflow interrupt.
2 | FUNDFL | RW | This is the Write FIFO Underflow interrupt.
1 | THR | RW | This is the FIFO Threshold interrupt.
0 | CMDCMP | RW | This is the Command Complete interrupt.

### INTSTAT - IO Master Interrupts: Status

### Address:

Instance 0 Address: | 0x50004204
Instance 1 Address: | 0x50005204

### Description:

Read bits from this register to discover the cause of a recent interrupt.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ARB 0x0 | STOP 0x0 | START 0x0 | ICMD 0x0 | IACC 0x0 | WTLEN 0x0 | NAK 0x0 | FOVFL 0x0 | FUNDFL 0x0 | THR 0x0 | CMDCMP 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED
10 | ARB | RW | This is the arbitration loss interrupt.
9 | STOP | RW | This is the STOP command interrupt.
8 | START | RW | This is the START command interrupt.
7 | ICMD | RW | This is the illegal command interrupt.
6 | IACC | RW | This is the illegal FIFO access interrupt.
5 | WTLEN | RW | This is the write length mismatch interrupt.
4 | NAK | RW | This is the I2C NAK interrupt.
3 | FOVFL | RW | This is the Read FIFO Overflow interrupt.
2 | FUNDFL | RW | This is the Write FIFO Underflow interrupt.
1 | THR | RW | This is the FIFO Threshold interrupt.
0 | CMDCMP | RW | This is the Command Complete interrupt.

### INTCLR - IO Master Interrupts: Clear

### Address:

Instance 0 Address: | 0x50004208
Instance 1 Address: | 0x50005208

### Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ARB 0x0 | STOP 0x0 | START 0x0 | ICMD 0x0 | IACC 0x0 | WTLEN 0x0 | NAK 0x0 | FOVFL 0x0 | FUNDFL 0x0 | THR 0x0 | CMDCMP 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED
10 | ARB | RW | This is the arbitration loss interrupt.
9 | STOP | RW | This is the STOP command interrupt.
8 | START | RW | This is the START command interrupt.
7 | ICMD | RW | This is the illegal command interrupt.
6 | IACC | RW | This is the illegal FIFO access interrupt.
5 | WTLEN | RW | This is the write length mismatch interrupt.
4 | NAK | RW | This is the I2C NAK interrupt.
3 | FOVFL | RW | This is the Read FIFO Overflow interrupt.
2 | FUNDFL | RW | This is the Write FIFO Underflow interrupt.
1 | THR | RW | This is the FIFO Threshold interrupt.
0 | CMDCMP | RW | This is the Command Complete interrupt.

### INTSET - IO Master Interrupts: Set

### Address:

Instance 0 Address: | 0x5000420C
Instance 1 Address: | 0x5000520C

### Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ARB 0x0 | STOP 0x0 | START 0x0 | ICMD 0x0 | IACC 0x0 | WTLEN 0x0 | NAK 0x0 | FOVFL 0x0 | FUNDFL 0x0 | THR 0x0 | CMDCMP 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED
10 | ARB | RW | This is the arbitration loss interrupt.
9 | STOP | RW | This is the STOP command interrupt.
8 | START | RW | This is the START command interrupt.
7 | ICMD | RW | This is the illegal command interrupt.
6 | IACC | RW | This is the illegal FIFO access interrupt.
5 | WTLEN | RW | This is the write length mismatch interrupt.
4 | NAK | RW | This is the I2C NAK interrupt.
3 | FOVFL | RW | This is the Read FIFO Overflow interrupt.
2 | FUNDFL | RW | This is the Write FIFO Underflow interrupt.
1 | THR | RW | This is the FIFO Threshold interrupt.
0 | CMDCMP | RW | This is the Command Complete interrupt.