| Apollo Register Documentation v2.2.0

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CTIMER - Counter/Timer

### CTIMER Register Index

0x00000000: | TMR0 - Counter/Timer Register
0x00000004: | CMPRA0 - Counter/Timer A0 Compare Registers
0x00000008: | CMPRB0 - Counter/Timer B0 Compare Registers
0x0000000C: | CTRL0 - Counter/Timer Control
0x00000010: | TMR1 - Counter/Timer Register
0x00000014: | CMPRA1 - Counter/Timer A1 Compare Registers
0x00000018: | CMPRB1 - Counter/Timer B1 Compare Registers
0x0000001C: | CTRL1 - Counter/Timer Control
0x00000020: | TMR2 - Counter/Timer Register
0x00000024: | CMPRA2 - Counter/Timer A2 Compare Registers
0x00000028: | CMPRB2 - Counter/Timer B2 Compare Registers
0x0000002C: | CTRL2 - Counter/Timer Control
0x00000030: | TMR3 - Counter/Timer Register
0x00000034: | CMPRA3 - Counter/Timer A3 Compare Registers
0x00000038: | CMPRB3 - Counter/Timer B3 Compare Registers
0x0000003C: | CTRL3 - Counter/Timer Control
0x00000100: | STCFG - Configuration Register
0x00000104: | STTMR - System Timer Count Register (Real Time Counter)
0x00000108: | CAPTURE_CONTROL - Capture Control Register
0x00000110: | SCMPR0 - Compare Register A
0x00000114: | SCMPR1 - Compare Register B
0x00000118: | SCMPR2 - Compare Register C
0x0000011C: | SCMPR3 - Compare Register D
0x00000120: | SCMPR4 - Compare Register E
0x00000124: | SCMPR5 - Compare Register F
0x00000128: | SCMPR6 - Compare Register G
0x0000012C: | SCMPR7 - Compare Register H
0x0000013C: | SDEBUG - Debug Register
0x00000140: | DBGRO - Debug Reasd Only Register
0x000001E0: | SCAPT0 - Capture Register A
0x000001E4: | SCAPT1 - Capture Register B
0x000001E8: | SCAPT2 - Capture Register C
0x000001EC: | SCAPT3 - Capture Register D
0x000001F0: | SNVR0 - System Timer NVRAM_A Register
0x000001F4: | SNVR1 - System Timer NVRAM_B Register
0x000001F8: | SNVR2 - System Timer NVRAM_C Register
0x00000200: | INTEN - Counter/Timer Interrupts: Enable
0x00000204: | INTSTAT - Counter/Timer Interrupts: Status
0x00000208: | INTCLR - Counter/Timer Interrupts: Clear
0x0000020C: | INTSET - Counter/Timer Interrupts: Set
0x00000300: | STMINTEN - STIMER Interrupt registers: Enable
0x00000304: | STMINTSTAT - STIMER Interrupt registers: Status
0x00000308: | STMINTCLR - STIMER Interrupt registers: Clear
0x0000030C: | STMINTSET - STIMER Interrupt registers: Set

### TMR0 - Counter/Timer Register

### Address:

Instance 0 Address: | 0x40008000

### Description:

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTTMRB0 0x0 | CTTMRA0 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CTTMRB0 | RO | Counter/Timer B0.
15:0 | CTTMRA0 | RO | Counter/Timer A0.

### CMPRA0 - Counter/Timer A0 Compare Registers

### Address:

Instance 0 Address: | 0x40008004

### Description:

Compare limits for timer half A.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1A0 0x0 | CMPR0A0 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1A0 | RW | Counter/Timer A0 Compare Register 1. Holds the upper limit for timer half A.
15:0 | CMPR0A0 | RW | Counter/Timer A0 Compare Register 0. Holds the lower limit for timer half A.

### CMPRB0 - Counter/Timer B0 Compare Registers

### Address:

Instance 0 Address: | 0x40008008

### Description:

Compare limits for timer half B.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1B0 0x0 | CMPR0B0 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1B0 | RW | Counter/Timer B0 Compare Register 1. Holds the upper limit for timer half B.
15:0 | CMPR0B0 | RW | Counter/Timer B0 Compare Register 0. Holds the lower limit for timer half B.

### CTRL0 - Counter/Timer Control

### Address:

Instance 0 Address: | 0x4000800C

### Description:

Control bit fields for both halves of timer 0.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTLINK0 0x0 | RSVD 0x0 | TMRB0PE 0x0 | TMRB0POL 0x0 | TMRB0CLR 0x0 | TMRB0IE1 0x0 | TMRB0IE0 0x0 | TMRB0FN 0x0 | TMRB0CLK 0x0 | TMRB0EN 0x0 | RSVD 0x0 | TMRA0PE 0x0 | TMRA0POL 0x0 | TMRA0CLR 0x0 | TMRA0IE1 0x0 | TMRA0IE0 0x0 | TMRA0FN 0x0 | TMRA0CLK 0x0 | TMRA0EN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | CTLINK0 | RW | Counter/Timer A0/B0 Link bit. TWO_16BIT_TIMERS = 0x0 - Use A0/B0 timers as two independent 16-bit timers (default). 32BIT_TIMER = 0x1 - Link A0/B0 timers into a single 32-bit timer.
30 | RSVD | RO | RESERVED
29 | TMRB0PE | RW | Counter/Timer B0 Output Enable bit. DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB0POL. EN = 0x1 - Enable counter/timer B0 to generate a signal on TMRPINB.
28 | TMRB0POL | RW | Counter/Timer B0 output polarity. NORMAL = 0x0 - The polarity of the TMRPINB0 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB0 pin is the inverse of the timer output.
27 | TMRB0CLR | RW | Counter/Timer B0 Clear bit. RUN = 0x0 - Allow counter/timer B0 to run CLEAR = 0x1 - Holds counter/timer B0 at 0x0000.
26 | TMRB0IE1 | RW | Counter/Timer B0 Interrupt Enable bit for COMPR1. DIS = 0x0 - Disable counter/timer B0 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B0 to generate an interrupt based on COMPR1.
25 | TMRB0IE0 | RW | Counter/Timer B0 Interrupt Enable bit for COMPR0. DIS = 0x0 - Disable counter/timer B0 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer B0 to generate an interrupt based on COMPR0
24:22 | TMRB0FN | RW | Counter/Timer B0 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B0, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B0, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B0, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B0, assert, count to CMPR1B0, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 | TMRB0CLK | RW | Counter/Timer B0 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINB. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKB = 0x10 - Clock source is buck converter stream B.
16 | TMRB0EN | RW | Counter/Timer B0 Enable bit. DIS = 0x0 - Counter/Timer B0 Disable. EN = 0x1 - Counter/Timer B0 Enable.
15:14 | RSVD | RO | RESERVED
13 | TMRA0PE | RW | Counter/Timer A0 Output Enable bit. DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA0POL. EN = 0x1 - Enable counter/timer B0 to generate a signal on TMRPINB.
12 | TMRA0POL | RW | Counter/Timer A0 output polarity. NORMAL = 0x0 - The polarity of the TMRPINA0 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA0 pin is the inverse of the timer output.
11 | TMRA0CLR | RW | Counter/Timer A0 Clear bit. RUN = 0x0 - Allow counter/timer A0 to run CLEAR = 0x1 - Holds counter/timer A0 at 0x0000.
10 | TMRA0IE1 | RW | Counter/Timer A0 Interrupt Enable bit based on COMPR1. DIS = 0x0 - Disable counter/timer A0 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A0 to generate an interrupt based on COMPR1.
9 | TMRA0IE0 | RW | Counter/Timer A0 Interrupt Enable bit based on COMPR0. DIS = 0x0 - Disable counter/timer A0 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A0 to generate an interrupt based on COMPR0.
8:6 | TMRA0FN | RW | Counter/Timer A0 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A0, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A0, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A0, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A0, assert, count to CMPR1A0, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 | TMRA0CLK | RW | Counter/Timer A0 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINA. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKA = 0x10 - Clock source is buck converter stream A.
0 | TMRA0EN | RW | Counter/Timer A0 Enable bit. DIS = 0x0 - Counter/Timer A0 Disable. EN = 0x1 - Counter/Timer A0 Enable.

### TMR1 - Counter/Timer Register

### Address:

Instance 0 Address: | 0x40008010

### Description:

This register holds the running time or event count, either for each 16 bit half or for the whole 32 bit count when the pair is linked.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTTMRB1 0x0 | CTTMRA1 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CTTMRB1 | RO | Counter/Timer B1.
15:0 | CTTMRA1 | RO | Counter/Timer A1.

### CMPRA1 - Counter/Timer A1 Compare Registers

### Address:

Instance 0 Address: | 0x40008014

### Description:

This register holds the compare limits for timer half A.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1A1 0x0 | CMPR0A1 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1A1 | RW | Counter/Timer A1 Compare Register 1.
15:0 | CMPR0A1 | RW | Counter/Timer A1 Compare Register 0.

### CMPRB1 - Counter/Timer B1 Compare Registers

### Address:

Instance 0 Address: | 0x40008018

### Description:

This register holds the compare limits for timer half B.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1B1 0x0 | CMPR0B1 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1B1 | RW | Counter/Timer B1 Compare Register 1.
15:0 | CMPR0B1 | RW | Counter/Timer B1 Compare Register 0.

### CTRL1 - Counter/Timer Control

### Address:

Instance 0 Address: | 0x4000801C

### Description:

Control bit fields for both halves of timer 0.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTLINK1 0x0 | RSVD 0x0 | TMRB1PE 0x0 | TMRB1POL 0x0 | TMRB1CLR 0x0 | TMRB1IE1 0x0 | TMRB1IE0 0x0 | TMRB1FN 0x0 | TMRB1CLK 0x0 | TMRB1EN 0x0 | RSVD 0x0 | TMRA1PE 0x0 | TMRA1POL 0x0 | TMRA1CLR 0x0 | TMRA1IE1 0x0 | TMRA1IE0 0x0 | TMRA1FN 0x0 | TMRA1CLK 0x0 | TMRA1EN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | CTLINK1 | RW | Counter/Timer A1/B1 Link bit. TWO_16BIT_TIMERS = 0x0 - Use A1/B1 timers as two independent 16-bit timers (default). 32BIT_TIMER = 0x1 - Link A1/B1 timers into a single 32-bit timer.
30 | RSVD | RO | RESERVED
29 | TMRB1PE | RW | Counter/Timer B1 Output Enable bit. DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB1POL. EN = 0x1 - Enable counter/timer B1 to generate a signal on TMRPINB.
28 | TMRB1POL | RW | Counter/Timer B1 output polarity. NORMAL = 0x0 - The polarity of the TMRPINB1 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB1 pin is the inverse of the timer output.
27 | TMRB1CLR | RW | Counter/Timer B1 Clear bit. RUN = 0x0 - Allow counter/timer B1 to run CLEAR = 0x1 - Holds counter/timer B1 at 0x0000.
26 | TMRB1IE1 | RW | Counter/Timer B1 Interrupt Enable bit for COMPR1. DIS = 0x0 - Disable counter/timer B1 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B1 to generate an interrupt based on COMPR1.
25 | TMRB1IE0 | RW | Counter/Timer B1 Interrupt Enable bit for COMPR0. DIS = 0x0 - Disable counter/timer B1 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer B1 to generate an interrupt based on COMPR0
24:22 | TMRB1FN | RW | Counter/Timer B1 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B1, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B1, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B1, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B1, assert, count to CMPR1B1, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 | TMRB1CLK | RW | Counter/Timer B1 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINB. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKB = 0x10 - Clock source is buck converter stream B.
16 | TMRB1EN | RW | Counter/Timer B1 Enable bit. DIS = 0x0 - Counter/Timer B1 Disable. EN = 0x1 - Counter/Timer B1 Enable.
15:14 | RSVD | RO | RESERVED
13 | TMRA1PE | RW | Counter/Timer A1 Output Enable bit. DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA1POL. EN = 0x1 - Enable counter/timer B1 to generate a signal on TMRPINB.
12 | TMRA1POL | RW | Counter/Timer A1 output polarity. NORMAL = 0x0 - The polarity of the TMRPINA1 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA1 pin is the inverse of the timer output.
11 | TMRA1CLR | RW | Counter/Timer A1 Clear bit. RUN = 0x0 - Allow counter/timer A1 to run CLEAR = 0x1 - Holds counter/timer A1 at 0x0000.
10 | TMRA1IE1 | RW | Counter/Timer A1 Interrupt Enable bit based on COMPR1. DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR1.
9 | TMRA1IE0 | RW | Counter/Timer A1 Interrupt Enable bit based on COMPR0. DIS = 0x0 - Disable counter/timer A1 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A1 to generate an interrupt based on COMPR0.
8:6 | TMRA1FN | RW | Counter/Timer A1 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A1, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A1, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A1, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A1, assert, count to CMPR1A1, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 | TMRA1CLK | RW | Counter/Timer A1 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINA. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKA = 0x10 - Clock source is buck converter stream A.
0 | TMRA1EN | RW | Counter/Timer A1 Enable bit. DIS = 0x0 - Counter/Timer A1 Disable. EN = 0x1 - Counter/Timer A1 Enable.

### TMR2 - Counter/Timer Register

### Address:

Instance 0 Address: | 0x40008020

### Description:

Counter/Timer Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTTMRB2 0x0 | CTTMRA2 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CTTMRB2 | RO | Counter/Timer B2.
15:0 | CTTMRA2 | RO | Counter/Timer A2.

### CMPRA2 - Counter/Timer A2 Compare Registers

### Address:

Instance 0 Address: | 0x40008024

### Description:

This register holds the compare limits for timer half A.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1A2 0x0 | CMPR0A2 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1A2 | RW | Counter/Timer A2 Compare Register 1.
15:0 | CMPR0A2 | RW | Counter/Timer A2 Compare Register 0.

### CMPRB2 - Counter/Timer B2 Compare Registers

### Address:

Instance 0 Address: | 0x40008028

### Description:

This register holds the compare limits for timer half B.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1B2 0x0 | CMPR0B2 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1B2 | RW | Counter/Timer B2 Compare Register 1.
15:0 | CMPR0B2 | RW | Counter/Timer B2 Compare Register 0.

### CTRL2 - Counter/Timer Control

### Address:

Instance 0 Address: | 0x4000802C

### Description:

This register holds the control bit fields for both halves of timer 2.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTLINK2 0x0 | RSVD 0x0 | TMRB2PE 0x0 | TMRB2POL 0x0 | TMRB2CLR 0x0 | TMRB2IE1 0x0 | TMRB2IE0 0x0 | TMRB2FN 0x0 | TMRB2CLK 0x0 | TMRB2EN 0x0 | RSVD 0x0 | TMRA2PE 0x0 | TMRA2POL 0x0 | TMRA2CLR 0x0 | TMRA2IE1 0x0 | TMRA2IE0 0x0 | TMRA2FN 0x0 | TMRA2CLK 0x0 | TMRA2EN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | CTLINK2 | RW | Counter/Timer A2/B2 Link bit. TWO_16BIT_TIMERS = 0x0 - Use A2/B2 timers as two independent 16-bit timers (default). 32BIT_TIMER = 0x1 - Link A2/B2 timers into a single 32-bit timer.
30 | RSVD | RO | RESERVED
29 | TMRB2PE | RW | Counter/Timer B2 Output Enable bit. DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB2POL. EN = 0x1 - Enable counter/timer B2 to generate a signal on TMRPINB.
28 | TMRB2POL | RW | Counter/Timer B2 output polarity. NORMAL = 0x0 - The polarity of the TMRPINB2 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB2 pin is the inverse of the timer output.
27 | TMRB2CLR | RW | Counter/Timer B2 Clear bit. RUN = 0x0 - Allow counter/timer B2 to run CLEAR = 0x1 - Holds counter/timer B2 at 0x0000.
26 | TMRB2IE1 | RW | Counter/Timer B2 Interrupt Enable bit for COMPR1. DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COMPR1.
25 | TMRB2IE0 | RW | Counter/Timer B2 Interrupt Enable bit for COMPR0. DIS = 0x0 - Disable counter/timer B2 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer B2 to generate an interrupt based on COMPR0
24:22 | TMRB2FN | RW | Counter/Timer B2 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B2, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B2, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B2, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B2, assert, count to CMPR1B2, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 | TMRB2CLK | RW | Counter/Timer B2 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINB. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKB = 0x10 - Clock source is buck converter stream B.
16 | TMRB2EN | RW | Counter/Timer B2 Enable bit. DIS = 0x0 - Counter/Timer B2 Disable. EN = 0x1 - Counter/Timer B2 Enable.
15:14 | RSVD | RO | RESERVED
13 | TMRA2PE | RW | Counter/Timer A2 Output Enable bit. DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA2POL. EN = 0x1 - Enable counter/timer B2 to generate a signal on TMRPINB.
12 | TMRA2POL | RW | Counter/Timer A2 output polarity. NORMAL = 0x0 - The polarity of the TMRPINA2 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA2 pin is the inverse of the timer output.
11 | TMRA2CLR | RW | Counter/Timer A2 Clear bit. RUN = 0x0 - Allow counter/timer A2 to run CLEAR = 0x1 - Holds counter/timer A2 at 0x0000.
10 | TMRA2IE1 | RW | Counter/Timer A2 Interrupt Enable bit based on COMPR1. DIS = 0x0 - Disable counter/timer A2 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A2 to generate an interrupt based on COMPR1.
9 | TMRA2IE0 | RW | Counter/Timer A2 Interrupt Enable bit based on COMPR0. DIS = 0x0 - Disable counter/timer A2 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A2 to generate an interrupt based on COMPR0.
8:6 | TMRA2FN | RW | Counter/Timer A2 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A2, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A2, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A2, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A2, assert, count to CMPR1A2, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 | TMRA2CLK | RW | Counter/Timer A2 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINA. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKA = 0x10 - Clock source is buck converter stream A.
0 | TMRA2EN | RW | Counter/Timer A2 Enable bit. DIS = 0x0 - Counter/Timer A2 Disable. EN = 0x1 - Counter/Timer A2 Enable.

### TMR3 - Counter/Timer Register

### Address:

Instance 0 Address: | 0x40008030

### Description:

Counter/Timer Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTTMRB3 0x0 | CTTMRA3 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CTTMRB3 | RO | Counter/Timer B3.
15:0 | CTTMRA3 | RO | Counter/Timer A3.

### CMPRA3 - Counter/Timer A3 Compare Registers

### Address:

Instance 0 Address: | 0x40008034

### Description:

This register holds the compare limits for timer half A.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1A3 0x0 | CMPR0A3 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1A3 | RW | Counter/Timer A3 Compare Register 1.
15:0 | CMPR0A3 | RW | Counter/Timer A3 Compare Register 0.

### CMPRB3 - Counter/Timer B3 Compare Registers

### Address:

Instance 0 Address: | 0x40008038

### Description:

This register holds the compare limits for timer half B.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CMPR1B3 0x0 | CMPR0B3 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | CMPR1B3 | RW | Counter/Timer B3 Compare Register 1.
15:0 | CMPR0B3 | RW | Counter/Timer B3 Compare Register 0.

### CTRL3 - Counter/Timer Control

### Address:

Instance 0 Address: | 0x4000803C

### Description:

This register holds the control bit fields for both halves of timer 3.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CTLINK3 0x0 | RSVD 0x0 | TMRB3PE 0x0 | TMRB3POL 0x0 | TMRB3CLR 0x0 | TMRB3IE1 0x0 | TMRB3IE0 0x0 | TMRB3FN 0x0 | TMRB3CLK 0x0 | TMRB3EN 0x0 | ADCEN 0x0 | RSVD 0x0 | TMRA3PE 0x0 | TMRA3POL 0x0 | TMRA3CLR 0x0 | TMRA3IE1 0x0 | TMRA3IE0 0x0 | TMRA3FN 0x0 | TMRA3CLK 0x0 | TMRA3EN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | CTLINK3 | RW | Counter/Timer A3/B3 Link bit. TWO_16BIT_TIMERS = 0x0 - Use A3/B3 timers as two independent 16-bit timers (default). 32BIT_TIMER = 0x1 - Link A3/B3 timers into a single 32-bit timer.
30 | RSVD | RO | RESERVED
29 | TMRB3PE | RW | Counter/Timer B3 Output Enable bit. DIS = 0x0 - Counter/Timer B holds the TMRPINB signal at the value TMRB3POL. EN = 0x1 - Enable counter/timer B3 to generate a signal on TMRPINB.
28 | TMRB3POL | RW | Counter/Timer B3 output polarity. NORMAL = 0x0 - The polarity of the TMRPINB3 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINB3 pin is the inverse of the timer output.
27 | TMRB3CLR | RW | Counter/Timer B3 Clear bit. RUN = 0x0 - Allow counter/timer B3 to run CLEAR = 0x1 - Holds counter/timer B3 at 0x0000.
26 | TMRB3IE1 | RW | Counter/Timer B3 Interrupt Enable bit for COMPR1. DIS = 0x0 - Disable counter/timer B3 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer B3 to generate an interrupt based on COMPR1.
25 | TMRB3IE0 | RW | Counter/Timer B3 Interrupt Enable bit for COMPR0. DIS = 0x0 - Disable counter/timer B3 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer B3 to generate an interrupt based on COMPR0
24:22 | TMRB3FN | RW | Counter/Timer B3 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0B3, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0B3, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0B3, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0B3, assert, count to CMPR1B3, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
21:17 | TMRB3CLK | RW | Counter/Timer B3 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINB. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKB = 0x10 - Clock source is buck converter stream B.
16 | TMRB3EN | RW | Counter/Timer B3 Enable bit. DIS = 0x0 - Counter/Timer B3 Disable. EN = 0x1 - Counter/Timer B3 Enable.
15 | ADCEN | RW | Special Timer A3 enable for ADC function.
14 | RSVD | RO | RESERVED
13 | TMRA3PE | RW | Counter/Timer A3 Output Enable bit. DIS = 0x0 - Counter/Timer A holds the TMRPINA signal at the value TMRA3POL. EN = 0x1 - Enable counter/timer B3 to generate a signal on TMRPINB.
12 | TMRA3POL | RW | Counter/Timer A3 output polarity. NORMAL = 0x0 - The polarity of the TMRPINA3 pin is the same as the timer output. INVERTED = 0x1 - The polarity of the TMRPINA3 pin is the inverse of the timer output.
11 | TMRA3CLR | RW | Counter/Timer A3 Clear bit. RUN = 0x0 - Allow counter/timer A3 to run CLEAR = 0x1 - Holds counter/timer A3 at 0x0000.
10 | TMRA3IE1 | RW | Counter/Timer A3 Interrupt Enable bit based on COMPR1. DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR1. EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR1.
9 | TMRA3IE0 | RW | Counter/Timer A3 Interrupt Enable bit based on COMPR0. DIS = 0x0 - Disable counter/timer A3 from generating an interrupt based on COMPR0. EN = 0x1 - Enable counter/timer A3 to generate an interrupt based on COMPR0.
8:6 | TMRA3FN | RW | Counter/Timer A3 Function Select. SINGLECOUNT = 0x0 - Single count (output toggles and sticks). Count to CMPR0A3, stop. REPEATEDCOUNT = 0x1 - Repeated count (periodic 1-clock-cycle-wide pulses). Count to CMPR0A3, restart. PULSE_ONCE = 0x2 - Pulse once (aka one-shot). Count to CMPR0A3, assert, count to CMPR1B, deassert, stop. PULSE_CONT = 0x3 - Pulse continously. Count to CMPR0A3, assert, count to CMPR1A3, deassert, restart. CONTINUOUS = 0x4 - Continuous run (aka Free Run). Count continuously.
5:1 | TMRA3CLK | RW | Counter/Timer A3 Clock Select. TMRPIN = 0x0 - Clock source is TMRPINA. HFRC = 0x1 - Clock source is the HFRC / 4 HFRC_DIV8 = 0x2 - Clock source is HFRC / 16 HFRC_DIV128 = 0x3 - Clock source is HFRC / 256 HFRC_DIV512 = 0x4 - Clock source is HFRC / 1024 HFRC_DIV2K = 0x5 - Clock source is HFRC / 4096 XT = 0x6 - Clock source is the XT (uncalibrated). XT_DIV2 = 0x7 - Clock source is XT / 2 XT_DIV16 = 0x8 - Clock source is XT / 16 XT_DIV256 = 0x9 - Clock source is XT / 124 LFRC_DIV2 = 0xA - Clock source is LFRC / 2 LFRC_DIV32 = 0xB - Clock source is LFRC / 32 LFRC_DIV1K = 0xC - Clock source is LFRC / 1024 LFRC = 0xD - Clock source is LFRC RTC_100HZ = 0xE - Clock source is 100 Hz from the current RTC oscillator. HCLK = 0xF - Clock source is HCLK. BUCKA = 0x10 - Clock source is buck converter stream A.
0 | TMRA3EN | RW | Counter/Timer A3 Enable bit. DIS = 0x0 - Counter/Timer A3 Disable. EN = 0x1 - Counter/Timer A3 Enable.

### STCFG - Configuration Register

### Address:

Instance 0 Address: | 0x40008100

### Description:

The STIMER Configuration Register contains the software control for selecting the clock divider and source feeding the system timer.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
FREEZE 0x1 | CLEAR 0x0 | RSVD 0x0 | COMPARE_H_EN 0x0 | COMPARE_G_EN 0x0 | COMPARE_F_EN 0x0 | COMPARE_E_EN 0x0 | COMPARE_D_EN 0x0 | COMPARE_C_EN 0x0 | COMPARE_B_EN 0x0 | COMPARE_A_EN 0x0 | RSVD 0x0 | CLKSEL 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | FREEZE | RW | Set this bit to one to freeze the clock input to the COUNTER register. Once frozen, the value can be safely written from the MCU. Unfreeze to resume. THAW = 0x0 - Let the COUNTER register run on its input clock. FREEZE = 0x1 - Stop the COUNTER register for loading.
30 | CLEAR | RW | Set this bit to one to clear the System Timer register. RUN = 0x0 - Let the COUNTER register run on its input clock. CLEAR = 0x1 - Stop the COUNTER register for loading.
29:16 | RSVD | RO | RESERVED.
15 | COMPARE_H_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare H disabled. ENABLE = 0x1 - Compare H enabled.
14 | COMPARE_G_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare G disabled. ENABLE = 0x1 - Compare G enabled.
13 | COMPARE_F_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare F disabled. ENABLE = 0x1 - Compare F enabled.
12 | COMPARE_E_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare E disabled. ENABLE = 0x1 - Compare E enabled.
11 | COMPARE_D_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare D disabled. ENABLE = 0x1 - Compare D enabled.
10 | COMPARE_C_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare C disabled. ENABLE = 0x1 - Compare C enabled.
9 | COMPARE_B_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare B disabled. ENABLE = 0x1 - Compare B enabled.
8 | COMPARE_A_EN | RW | Selects whether compare is enabled for the corresponding SCMPR register. If compare is enabled, the interrupt status is set once the comparision is met. DISABLE = 0x0 - Compare A disabled. ENABLE = 0x1 - Compare A enabled.
7:4 | RSVD | RO | RESERVED.
3:0 | CLKSEL | RW | Selects an appropriate clock source and divider to use for the System Timer clock. NOCLK = 0x0 - No clock enabled. HFRC_DIV16 = 0x1 - 3MHz from the HFRC clock divider. HFRC_DIV256 = 0x2 - 187.5KHz from the HFRC clock divider. XTAL_DIV1 = 0x3 - 32768Hz from the crystal oscillator. XTAL_DIV2 = 0x4 - 16384Hz from the crystal oscillator. XTAL_DIV32 = 0x5 - 1024Hz from the crystal oscillator. LFRC_DIV1 = 0x6 - Approximately 1KHz from the LFRC oscillator (uncalibrated). CTIMER0A = 0x7 - Use CTIMER 0 section A as a prescaler for the clock source. CTIMER0B = 0x8 - Use CTIMER 0 section B (or A and B linked together) as a prescaler for the clock source.

### STTMR - System Timer Count Register (Real Time Counter)

### Address:

Instance 0 Address: | 0x40008104

### Description:

The COUNTER Register contains the running count of time as maintained by incrementing for every rising clock edge of the clock source selected in the configuration register. It is this counter value that captured in the capture registers and it is this counter value that is compared against the various compare registers. Writing to this register will ultimately set the COUNTER VALUE to the specified value. WARNING there is an asynchronous clock crossing on the read and write path which can add several STIMER clocks of uncertainty to reading or setting. Use the FREEZE bit in the DEBUG register to safely write to this register for diagnostic purposes.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RO | Value of the 32-bit counter as it ticks over.

### CAPTURE_CONTROL - Capture Control Register

### Address:

Instance 0 Address: | 0x40008108

### Description:

The STIMER Capture Control Register controls each of the 4 capture registers. It selects their GPIO pin number for a trigger source, enables a capture operation and sets the input polarity for the capture. NOTE: 8-bit writes can control individual capture registers atomically.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CAPTURE_D 0x0 | CAPTURE_C 0x0 | CAPTURE_B 0x0 | CAPTURE_A 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:4 | RSVD | RO | RESERVED.
3 | CAPTURE_D | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled.
2 | CAPTURE_C | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled.
1 | CAPTURE_B | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled.
0 | CAPTURE_A | RW | Selects whether capture is enabled for the specified capture register. DISABLE = 0x0 - Capture function disabled. ENABLE = 0x1 - Capture function enabled.

### SCMPR0 - Compare Register A

### Address:

Instance 0 Address: | 0x40008110

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR1 - Compare Register B

### Address:

Instance 0 Address: | 0x40008114

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR2 - Compare Register C

### Address:

Instance 0 Address: | 0x40008118

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR3 - Compare Register D

### Address:

Instance 0 Address: | 0x4000811C

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR4 - Compare Register E

### Address:

Instance 0 Address: | 0x40008120

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR5 - Compare Register F

### Address:

Instance 0 Address: | 0x40008124

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR6 - Compare Register G

### Address:

Instance 0 Address: | 0x40008128

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise. Reading this register shows the COUNTER value at which this interrupt will occur.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SCMPR7 - Compare Register H

### Address:

Instance 0 Address: | 0x4000812C

### Description:

The VALUE in this bit field is used to compare against the VALUE in the COUNTER register. If the match criterion in the configuration register is met then a corresponding interrupt status bit is set. The match criterion is defined as COUNTER equal to COMPARE or optionally COUNTER great than or equal to COMPARE. To establish a desired value in this COMPARE register, write the number of ticks in the future to this register to indicate when to interrupt. The hardware does the addition to the COUNTER value in the STIMER clock domain so that the math is precise.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Compare this value to the value in the COUNTER register according to the match criterion, as selected in the MATCH bit field in the CFG register.

### SDEBUG - Debug Register

### Address:

Instance 0 Address: | 0x4000813C

### Description:

The debug register provides diagnostic control of the STIMER block. It can freeze the counter register so that it can be safely written for test purposes. The designer will add additional internal state read back bit fields to this register during design, such as state machine bits, enable bits and information that would otherwise be unobservable in real silicon.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | FSM_RO 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:8 | RSVD | RO | RESERVED.
7:0 | FSM_RO | RO | The designer should wire in interest read only observability bits here.

### DBGRO - Debug Reasd Only Register

### Address:

Instance 0 Address: | 0x40008140

### Description:

The STIMER debug read only register provides additional debug information regarding the existence of the STIMER in an MCU and also indicates which revision of the block is present.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0xc001d00d

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RO | Always read back the fixed value of 0xc001d00d to add in validation of the block and to test the bus connections to the block. Subsequent version of this block will read a different 32-bit pattern

### SCAPT0 - Capture Register A

### Address:

Instance 0 Address: | 0x400081E0

### Description:

The STIMER capture Register A grabs the VALUE in the COUNTER register whenever capture condition (event) A is asserted. This register holds a time stamp for the event.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

### SCAPT1 - Capture Register B

### Address:

Instance 0 Address: | 0x400081E4

### Description:

The STIMER capture Register B grabs the VALUE in the COUNTER register whenever capture condition (event) B is asserted. This register holds a time stamp for the event.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

### SCAPT2 - Capture Register C

### Address:

Instance 0 Address: | 0x400081E8

### Description:

The STIMER capture Register C grabs the VALUE in the COUNTER register whenever capture condition (event) C is asserted. This register holds a time stamp for the event.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

### SCAPT3 - Capture Register D

### Address:

Instance 0 Address: | 0x400081EC

### Description:

The STIMER capture Register D grabs the VALUE in the COUNTER register whenever capture condition (event) D is asserted. This register holds a time stamp for the event.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RO | Whenever the event is detected, the value in the COUNTER is copied into this register and the corresponding interrupt status bit is set.

### SNVR0 - System Timer NVRAM_A Register

### Address:

Instance 0 Address: | 0x400081F0

### Description:

The NVRAM_A Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Value of the 32-bit counter as it ticks over.

### SNVR1 - System Timer NVRAM_B Register

### Address:

Instance 0 Address: | 0x400081F4

### Description:

The NVRAM_B Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Value of the 32-bit counter as it ticks over.

### SNVR2 - System Timer NVRAM_C Register

### Address:

Instance 0 Address: | 0x400081F8

### Description:

The NVRAM_C Register contains a portion of the stored epoch offset associated with the time in the COUNTER register. This register is only reset by POI not by HRESETn. Its contents are intended to survive all reset level except POI and full power cycles.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
VALUE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | VALUE | RW | Value of the 32-bit counter as it ticks over.

### INTEN - Counter/Timer Interrupts: Enable

### Address:

Instance 0 Address: | 0x40008200

### Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CTMRB3C1INT 0x0 | CTMRA3C1INT 0x0 | CTMRB2C1INT 0x0 | CTMRA2C1INT 0x0 | CTMRB1C1INT 0x0 | CTMRA1C1INT 0x0 | CTMRB0C1INT 0x0 | CTMRA0C1INT 0x0 | CTMRB3C0INT 0x0 | CTMRA3C0INT 0x0 | CTMRB2C0INT 0x0 | CTMRA2C0INT 0x0 | CTMRB1C0INT 0x0 | CTMRA1C0INT 0x0 | CTMRB0C0INT 0x0 | CTMRA0C0INT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | RSVD | RO | RESERVED
15 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1.
14 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1.
13 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1.
12 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1.
11 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1.
10 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1.
9 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1.
8 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1.
7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0.
6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0.
5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0.
4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0.
3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0.
2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0.
1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0.
0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0.

### INTSTAT - Counter/Timer Interrupts: Status

### Address:

Instance 0 Address: | 0x40008204

### Description:

Read bits from this register to discover the cause of a recent interrupt.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CTMRB3C1INT 0x0 | CTMRA3C1INT 0x0 | CTMRB2C1INT 0x0 | CTMRA2C1INT 0x0 | CTMRB1C1INT 0x0 | CTMRA1C1INT 0x0 | CTMRB0C1INT 0x0 | CTMRA0C1INT 0x0 | CTMRB3C0INT 0x0 | CTMRA3C0INT 0x0 | CTMRB2C0INT 0x0 | CTMRA2C0INT 0x0 | CTMRB1C0INT 0x0 | CTMRA1C0INT 0x0 | CTMRB0C0INT 0x0 | CTMRA0C0INT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | RSVD | RO | RESERVED
15 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1.
14 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1.
13 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1.
12 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1.
11 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1.
10 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1.
9 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1.
8 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1.
7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0.
6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0.
5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0.
4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0.
3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0.
2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0.
1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0.
0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0.

### INTCLR - Counter/Timer Interrupts: Clear

### Address:

Instance 0 Address: | 0x40008208

### Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CTMRB3C1INT 0x0 | CTMRA3C1INT 0x0 | CTMRB2C1INT 0x0 | CTMRA2C1INT 0x0 | CTMRB1C1INT 0x0 | CTMRA1C1INT 0x0 | CTMRB0C1INT 0x0 | CTMRA0C1INT 0x0 | CTMRB3C0INT 0x0 | CTMRA3C0INT 0x0 | CTMRB2C0INT 0x0 | CTMRA2C0INT 0x0 | CTMRB1C0INT 0x0 | CTMRA1C0INT 0x0 | CTMRB0C0INT 0x0 | CTMRA0C0INT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | RSVD | RO | RESERVED
15 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1.
14 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1.
13 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1.
12 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1.
11 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1.
10 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1.
9 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1.
8 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1.
7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0.
6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0.
5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0.
4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0.
3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0.
2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0.
1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0.
0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0.

### INTSET - Counter/Timer Interrupts: Set

### Address:

Instance 0 Address: | 0x4000820C

### Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CTMRB3C1INT 0x0 | CTMRA3C1INT 0x0 | CTMRB2C1INT 0x0 | CTMRA2C1INT 0x0 | CTMRB1C1INT 0x0 | CTMRA1C1INT 0x0 | CTMRB0C1INT 0x0 | CTMRA0C1INT 0x0 | CTMRB3C0INT 0x0 | CTMRA3C0INT 0x0 | CTMRB2C0INT 0x0 | CTMRA2C0INT 0x0 | CTMRB1C0INT 0x0 | CTMRA1C0INT 0x0 | CTMRB0C0INT 0x0 | CTMRA0C0INT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | RSVD | RO | RESERVED
15 | CTMRB3C1INT | RW | Counter/Timer B3 interrupt based on COMPR1.
14 | CTMRA3C1INT | RW | Counter/Timer A3 interrupt based on COMPR1.
13 | CTMRB2C1INT | RW | Counter/Timer B2 interrupt based on COMPR1.
12 | CTMRA2C1INT | RW | Counter/Timer A2 interrupt based on COMPR1.
11 | CTMRB1C1INT | RW | Counter/Timer B1 interrupt based on COMPR1.
10 | CTMRA1C1INT | RW | Counter/Timer A1 interrupt based on COMPR1.
9 | CTMRB0C1INT | RW | Counter/Timer B0 interrupt based on COMPR1.
8 | CTMRA0C1INT | RW | Counter/Timer A0 interrupt based on COMPR1.
7 | CTMRB3C0INT | RW | Counter/Timer B3 interrupt based on COMPR0.
6 | CTMRA3C0INT | RW | Counter/Timer A3 interrupt based on COMPR0.
5 | CTMRB2C0INT | RW | Counter/Timer B2 interrupt based on COMPR0.
4 | CTMRA2C0INT | RW | Counter/Timer A2 interrupt based on COMPR0.
3 | CTMRB1C0INT | RW | Counter/Timer B1 interrupt based on COMPR0.
2 | CTMRA1C0INT | RW | Counter/Timer A1 interrupt based on COMPR0.
1 | CTMRB0C0INT | RW | Counter/Timer B0 interrupt based on COMPR0.
0 | CTMRA0C0INT | RW | Counter/Timer A0 interrupt based on COMPR0.

### STMINTEN - STIMER Interrupt registers: Enable

### Address:

Instance 0 Address: | 0x40008300

### Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CAPTURED 0x0 | CAPTUREC 0x0 | CAPTUREB 0x0 | CAPTUREA 0x0 | OVERFLOW 0x0 | COMPAREH 0x0 | COMPAREG 0x0 | COMPAREF 0x0 | COMPAREE 0x0 | COMPARED 0x0 | COMPAREC 0x0 | COMPAREB 0x0 | COMPAREA 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:13 | RSVD | RO | RESERVED.
12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.

### STMINTSTAT - STIMER Interrupt registers: Status

### Address:

Instance 0 Address: | 0x40008304

### Description:

Read bits from this register to discover the cause of a recent interrupt.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CAPTURED 0x0 | CAPTUREC 0x0 | CAPTUREB 0x0 | CAPTUREA 0x0 | OVERFLOW 0x0 | COMPAREH 0x0 | COMPAREG 0x0 | COMPAREF 0x0 | COMPAREE 0x0 | COMPARED 0x0 | COMPAREC 0x0 | COMPAREB 0x0 | COMPAREA 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:13 | RSVD | RO | RESERVED.
12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.

### STMINTCLR - STIMER Interrupt registers: Clear

### Address:

Instance 0 Address: | 0x40008308

### Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CAPTURED 0x0 | CAPTUREC 0x0 | CAPTUREB 0x0 | CAPTUREA 0x0 | OVERFLOW 0x0 | COMPAREH 0x0 | COMPAREG 0x0 | COMPAREF 0x0 | COMPAREE 0x0 | COMPARED 0x0 | COMPAREC 0x0 | COMPAREB 0x0 | COMPAREA 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:13 | RSVD | RO | RESERVED.
12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.

### STMINTSET - STIMER Interrupt registers: Set

### Address:

Instance 0 Address: | 0x4000830C

### Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CAPTURED 0x0 | CAPTUREC 0x0 | CAPTUREB 0x0 | CAPTUREA 0x0 | OVERFLOW 0x0 | COMPAREH 0x0 | COMPAREG 0x0 | COMPAREF 0x0 | COMPAREE 0x0 | COMPARED 0x0 | COMPAREC 0x0 | COMPAREB 0x0 | COMPAREA 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:13 | RSVD | RO | RESERVED.
12 | CAPTURED | RW | CAPTURE register D has grabbed the value in the counter CAPD_INT = 0x1 - Capture D interrupt status bit was set.
11 | CAPTUREC | RW | CAPTURE register C has grabbed the value in the counter CAPC_INT = 0x1 - CAPTURE C interrupt status bit was set.
10 | CAPTUREB | RW | CAPTURE register B has grabbed the value in the counter CAPB_INT = 0x1 - CAPTURE B interrupt status bit was set.
9 | CAPTUREA | RW | CAPTURE register A has grabbed the value in the counter CAPA_INT = 0x1 - CAPTURE A interrupt status bit was set.
8 | OVERFLOW | RW | COUNTER over flowed from 0xFFFFFFFF back to 0x00000000. OFLOW_INT = 0x1 - Overflow interrupt status bit was set.
7 | COMPAREH | RW | COUNTER is greater than or equal to COMPARE register H. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
6 | COMPAREG | RW | COUNTER is greater than or equal to COMPARE register G. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
5 | COMPAREF | RW | COUNTER is greater than or equal to COMPARE register F. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
4 | COMPAREE | RW | COUNTER is greater than or equal to COMPARE register E. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
3 | COMPARED | RW | COUNTER is greater than or equal to COMPARE register D. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
2 | COMPAREC | RW | COUNTER is greater than or equal to COMPARE register C. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
1 | COMPAREB | RW | COUNTER is greater than or equal to COMPARE register B. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.
0 | COMPAREA | RW | COUNTER is greater than or equal to COMPARE register A. COMPARED = 0x1 - COUNTER greater than or equal to COMPARE register.