| Apollo Register Documentation v2.2.0

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CLKGEN - Clock Generator

### CLKGEN Register Index

0x00000000: | CALXT - XT Oscillator Control
0x00000004: | CALRC - RC Oscillator Control
0x00000008: | ACALCTR - Autocalibration Counter
0x0000000C: | OCTRL - Oscillator Control
0x00000010: | CLKOUT - CLKOUT Frequency Select
0x00000014: | CLKKEY - Key Register for Clock Control Register
0x00000018: | CCTRL - HFRC Clock Control
0x0000001C: | STATUS - Clock Generator Status
0x00000020: | HFADJ - HFRC Adjustment
0x00000028: | CLOCKENSTAT - Clock Enable Status
0x0000002C: | CLOCKEN2STAT - Clock Enable Status
0x00000030: | CLOCKEN3STAT - Clock Enable Status
0x00000034: | FREQCTRL - HFRC Frequency Control register
0x0000003C: | BLEBUCKTONADJ - BLE BUCK TON ADJUST
0x00000100: | INTRPTEN - CLKGEN Interrupt Register: Enable
0x00000104: | INTRPTSTAT - CLKGEN Interrupt Register: Status
0x00000108: | INTRPTCLR - CLKGEN Interrupt Register: Clear
0x0000010C: | INTRPTSET - CLKGEN Interrupt Register: Set

### CALXT - XT Oscillator Control

### Address:

Instance 0 Address: | 0x40004000

### Description:

This is the XT Oscillator Calibration value. This value allows any derived XT clocks to be "calibrated". This means that the original 32KHz version of XT will not be changed, but a 16KHz version (divided down version) can be modified. This register value will add or subtract the number of cycles programmed in this register across a 32 seconds interval. For example, if a value of 100 is programmed in this register, then 100 additional clock cycles will be added into a 16KHz clock period across a 32 second interval.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CALXT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED
10:0 | CALXT | RW | XT Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 16KHz clock derived from the original 32KHz version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The maximum value that is effective is from -1024 to 1023.

### CALRC - RC Oscillator Control

### Address:

Instance 0 Address: | 0x40004004

### Description:

This is the LFRC Calibration value. Similar to the XT calibration, it allows the derived LFRC clock to be calibrated. The original 1024Hz clock source will not change, but a 512Hz version (divided down version) can be modified. This register will add or subtract the number of cycles programmed in this register across a 1024 seconds interval. For example, if a value of 200 is programmed in this register, then 200 additional clocks will be added into the 512Hz derived clock across a 1024 seconds interval.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CALRC 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:18 | RSVD | RO | RESERVED
17:0 | CALRC | RW | LFRC Oscillator calibration value. This register will enable the hardware to increase or decrease the number of cycles in a 512 Hz clock derived from the original 1024 version. The most significant bit is the sign. A '1' is a reduction, and a '0' is an addition. This calibration value will add or reduce the number of cycles programmed here across a 32 second interval. The range is from -131072 (decimal) to 131071 (decimal). This register is normally used in conjuction with ACALCTR register. The CALRC register will load the ACALCTR register (bits 17:0) if the ACALCTR register is set to measure the LFRC with the XT clock.

### ACALCTR - Autocalibration Counter

### Address:

Instance 0 Address: | 0x40004008

### Description:

This register can be used for 2 purposes. The first is to calibrate the LFRC clock using the XT clock source. The second is to measure an internal clock signal relative to the external clock. In that case, the ACALCTR will show the multiple of the external clock with respect to the internal clock signal. E.g. Fref = Fmeas x ACALCTR. Note that this register should not be confused with the HFRC Adjustment register, which is separately defined in CLKGEN_HFADJ register.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ACALCTR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:24 | RSVD | RO | RESERVED
23:0 | ACALCTR | RO | Autocalibration Counter result. Bits 17 down to 0 of this is feed directly to the CALRC register if ACAL register in OCTRL register is set to 1024SEC or 512SEC.

### OCTRL - Oscillator Control

### Address:

Instance 0 Address: | 0x4000400C

### Description:

This register includes controls for autocalibration in addition to the RTC oscillator controls.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ACAL 0x0 | OSEL 0x0 | FOS 0x0 | RSVD 0x0 | STOPRC 0x0 | STOPXT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED
10:8 | ACAL | RW | Autocalibration control. This selects the source to be used in the autocalibration flow. This flow can also be used to measure an internal clock against an external clock source, with the external clock normally used as the reference. DIS = 0x0 - Disable Autocalibration 1024SEC = 0x2 - Autocalibrate every 1024 seconds. Once autocalibration is done, an interrupt will be triggered at the end of 1024 seconds. 512SEC = 0x3 - Autocalibrate every 512 seconds. Once autocalibration is done, an interrupt will be trigged at the end of 512 seconds. XTFREQ = 0x6 - Frequency measurement using XT. The XT clock is normally considered much more accurate than the LFRC clock source. EXTFREQ = 0x7 - Frequency measurement using external clock.
7 | OSEL | RW | Selects the RTC oscillator (1 => LFRC, 0 => XT) RTC_XT = 0x0 - RTC uses the XT RTC_LFRC = 0x1 - RTC uses the LFRC
6 | FOS | RW | Oscillator switch on failure function. If this is set, then LFRC clock source will switch from XT to RC. DIS = 0x0 - Disable the oscillator switch on failure function. EN = 0x1 - Enable the oscillator switch on failure function.
5:2 | RSVD | RO | RESERVED
1 | STOPRC | RW | Stop the LFRC Oscillator to the RTC EN = 0x0 - Enable the LFRC Oscillator to drive the RTC STOP = 0x1 - Stop the LFRC Oscillator when driving the RTC
0 | STOPXT | RW | Stop the XT Oscillator to the RTC EN = 0x0 - Enable the XT Oscillator to drive the RTC STOP = 0x1 - Stop the XT Oscillator when driving the RTC

### CLKOUT - CLKOUT Frequency Select

### Address:

Instance 0 Address: | 0x40004010

### Description:

This register enables the CLKOUT to the GPIOs, and selects the clock source to that.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CKEN 0x0 | RSVD 0x0 | CKSEL 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:8 | RSVD | RO | RESERVED
7 | CKEN | RW | Enable the CLKOUT signal DIS = 0x0 - Disable CLKOUT EN = 0x1 - Enable CLKOUT
6 | RSVD | RO | RESERVED
5:0 | CKSEL | RW | CLKOUT signal select LFRC = 0x0 - LFRC XT_DIV2 = 0x1 - XT / 2 XT_DIV4 = 0x2 - XT / 4 XT_DIV8 = 0x3 - XT / 8 XT_DIV16 = 0x4 - XT / 16 XT_DIV32 = 0x5 - XT / 32 RTC_1Hz = 0x10 - 1 Hz as selected in RTC XT_DIV2M = 0x16 - XT / 2^21 XT = 0x17 - XT CG_100Hz = 0x18 - 100 Hz as selected in CLKGEN HFRC = 0x19 - HFRC HFRC_DIV4 = 0x1A - HFRC / 4 HFRC_DIV8 = 0x1B - HFRC / 8 HFRC_DIV16 = 0x1C - HFRC / 16 HFRC_DIV64 = 0x1D - HFRC / 64 HFRC_DIV128 = 0x1E - HFRC / 128 HFRC_DIV256 = 0x1F - HFRC / 256 HFRC_DIV512 = 0x20 - HFRC / 512 FLASH_CLK = 0x22 - Flash Clock LFRC_DIV2 = 0x23 - LFRC / 2 LFRC_DIV32 = 0x24 - LFRC / 32 LFRC_DIV512 = 0x25 - LFRC / 512 LFRC_DIV32K = 0x26 - LFRC / 32768 XT_DIV256 = 0x27 - XT / 256 XT_DIV8K = 0x28 - XT / 8192 XT_DIV64K = 0x29 - XT / 2^16 ULFRC_DIV16 = 0x2A - Uncal LFRC / 16 ULFRC_DIV128 = 0x2B - Uncal LFRC / 128 ULFRC_1Hz = 0x2C - Uncal LFRC / 1024 ULFRC_DIV4K = 0x2D - Uncal LFRC / 4096 ULFRC_DIV1M = 0x2E - Uncal LFRC / 2^20 HFRC_DIV64K = 0x2F - HFRC / 2^16 HFRC_DIV16M = 0x30 - HFRC / 2^24 LFRC_DIV1M = 0x31 - LFRC / 2^20 HFRCNE = 0x32 - HFRC (not autoenabled) HFRCNE_DIV8 = 0x33 - HFRC / 8 (not autoenabled) XTNE = 0x35 - XT (not autoenabled) XTNE_DIV16 = 0x36 - XT / 16 (not autoenabled) LFRCNE_DIV32 = 0x37 - LFRC / 32 (not autoenabled) LFRCNE = 0x39 - LFRC (not autoenabled) - Default for undefined values

### CLKKEY - Key Register for Clock Control Register

### Address:

Instance 0 Address: | 0x40004014

### Description:

Key Register for Clock Control Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CLKKEY 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | CLKKEY | RW | Key register value. Key = 0x47 - Key

### CCTRL - HFRC Clock Control

### Address:

Instance 0 Address: | 0x40004018

### Description:

This register controls the main divider for HFRC clock. If this is set, all internal HFRC clock sources are divided by 2.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CORESEL 0x1

Bits | Name | RW | Description
--- | --- | --- | ---
31:1 | RSVD | RO | RESERVED
0 | CORESEL | RW | Core Clock divisor HFRC = 0x0 - Core Clock is HFRC HFRC_DIV2 = 0x1 - Core Clock is HFRC / 2

### STATUS - Clock Generator Status

### Address:

Instance 0 Address: | 0x4000401C

### Description:

This register provides status to the XT oscillator and the source of the RTC.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OSCF 0x0 | OMODE 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:2 | RSVD | RO | RESERVED
1 | OSCF | RO | XT Oscillator is enabled but not oscillating
0 | OMODE | RO | Current RTC oscillator (1 => LFRC, 0 => XT). After an RTC oscillator change, it may take up to 2 seconds for this field to reflect the new oscillator.

### HFADJ - HFRC Adjustment

### Address:

Instance 0 Address: | 0x40004020

### Description:

This register controls the HFRC adjustment. The HFRC clock can change with temperature and process corners, and this register controls the HFRC adjustment logic which reduces the fluctuations to the clock.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | HFADJGAIN 0x1 | HFWARMUP 0x0 | HFXTADJ 0x5b8 | RSVD 0x0 | HFADJCK 0x0 | HFADJEN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:24 | RSVD | RO | RESERVED
23:21 | HFADJGAIN | RW | Gain control for HFRC adjustment Gain_of_1 = 0x0 - HF Adjust with Gain of 1 Gain_of_1_in_2 = 0x1 - HF Adjust with Gain of 0.5 Gain_of_1_in_4 = 0x2 - HF Adjust with Gain of 0.25 Gain_of_1_in_8 = 0x3 - HF Adjust with Gain of 0.125 Gain_of_1_in_16 = 0x4 - HF Adjust with Gain of 0.0625 Gain_of_1_in_32 = 0x5 - HF Adjust with Gain of 0.03125
20 | HFWARMUP | RW | XT warmup period for HFRC adjustment 1SEC = 0x0 - Autoadjust XT warmup period = 1-2 seconds 2SEC = 0x1 - Autoadjust XT warmup period = 2-4 seconds
19:8 | HFXTADJ | RW | Target HFRC adjustment value.
7:4 | RSVD | RO | RESERVED
3:1 | HFADJCK | RW | Repeat period for HFRC adjustment 4SEC = 0x0 - Autoadjust repeat period = 4 seconds 16SEC = 0x1 - Autoadjust repeat period = 16 seconds 32SEC = 0x2 - Autoadjust repeat period = 32 seconds 64SEC = 0x3 - Autoadjust repeat period = 64 seconds 128SEC = 0x4 - Autoadjust repeat period = 128 seconds 256SEC = 0x5 - Autoadjust repeat period = 256 seconds 512SEC = 0x6 - Autoadjust repeat period = 512 seconds 1024SEC = 0x7 - Autoadjust repeat period = 1024 seconds
0 | HFADJEN | RW | HFRC adjustment control DIS = 0x0 - Disable the HFRC adjustment EN = 0x1 - Enable the HFRC adjustment

### CLOCKENSTAT - Clock Enable Status

### Address:

Instance 0 Address: | 0x40004028

### Description:

This register provides the enable status to all the peripheral clocks.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CLOCKENSTAT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | CLOCKENSTAT | RO | Clock enable status ADC_CLKEN = 0x1 - Clock enable for the ADC. APBDMA_ACTIVITY_CLKEN = 0x2 - Clock enable for the APBDMA ACTIVITY APBDMA_AOH_CLKEN = 0x4 - Clock enable for the APBDMA AOH DOMAIN APBDMA_AOL_CLKEN = 0x8 - Clock enable for the APBDMA AOL DOMAIN APBDMA_APB_CLKEN = 0x10 - Clock enable for the APBDMA_APB APBDMA_BLEL_CLKEN = 0x20 - Clock enable for the APBDMA_BLEL APBDMA_HCPA_CLKEN = 0x40 - Clock enable for the APBDMA_HCPA APBDMA_HCPB_CLKEN = 0x80 - Clock enable for the APBDMA_HCPB APBDMA_HCPC_CLKEN = 0x100 - Clock enable for the APBDMA_HCPC APBDMA_MSPI_CLKEN = 0x200 - Clock enable for the APBDMA_MSPI APBDMA_PDM_CLKEN = 0x400 - Clock enable for the APBDMA_PDM BLEIF_CLK_CLKEN = 0x800 - Clock enable for the BLEIF BLEIF_CLK32K_CLKEN = 0x1000 - Clock enable for the BLEIF 32khZ CLOCK CTIMER_CLKEN = 0x2000 - Clock enable for the CTIMER BLOCK CTIMER0A_CLKEN = 0x4000 - Clock enable for the CTIMER0A CTIMER0B_CLKEN = 0x8000 - Clock enable for the CTIMER0B CTIMER1A_CLKEN = 0x10000 - Clock enable for the CTIMER1A CTIMER1B_CLKEN = 0x20000 - Clock enable for the CTIMER1B CTIMER2A_CLKEN = 0x40000 - Clock enable for the CTIMER2A CTIMER2B_CLKEN = 0x80000 - Clock enable for the CTIMER2B CTIMER3A_CLKEN = 0x100000 - Clock enable for the CTIMER3A CTIMER3B_CLKEN = 0x200000 - Clock enable for the CTIMER3B CTIMER4A_CLKEN = 0x400000 - Clock enable for the CTIMER4A CTIMER4B_CLKEN = 0x800000 - Clock enable for the CTIMER4B CTIMER5A_CLKEN = 0x1000000 - Clock enable for the CTIMER5A CTIMER5B_CLKEN = 0x2000000 - Clock enable for the CTIMER5B CTIMER6A_CLKEN = 0x4000000 - Clock enable for the CTIMER6A CTIMER6B_CLKEN = 0x8000000 - Clock enable for the CTIMER6B CTIMER7A_CLKEN = 0x10000000 - Clock enable for the CTIMER7A CTIMER7B_CLKEN = 0x20000000 - Clock enable for the CTIMER7B DAP_CLKEN = 0x40000000 - Clock enable for the DAP IOMSTRIFC0_CLKEN = 0x80000000 - Clock enable for the IOMSTRIFC0

### CLOCKEN2STAT - Clock Enable Status

### Address:

Instance 0 Address: | 0x4000402C

### Description:

This is a continuation of the clock enable status.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CLOCKEN2STAT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | CLOCKEN2STAT | RO | Clock enable status 2 IOMSTRIFC1_CLKEN = 0x1 - Clock enable for the IO MASTER 1 IFC INTERFACE IOMSTRIFC2_CLKEN = 0x2 - Clock enable for the IO MASTER 2 IFC INTERFACE IOMSTRIFC3_CLKEN = 0x4 - Clock enable for the IO MASTER 3 IFC INTERFACE IOMSTRIFC4_CLKEN = 0x8 - Clock enable for the IO MASTER 4 IFC INTERFACE IOMSTRIFC5_CLKEN = 0x10 - Clock enable for the IO MASTER 5 IFC INTERFACE PDM_CLKEN = 0x20 - Clock enable for the PDM PDMIFC_CLKEN = 0x40 - Clock enable for the PDM INTERFACE PWRCTRL_CLKEN = 0x80 - Clock enable for the PWRCTRL PWRCTRL_COUNT_CLKEN = 0x100 - Clock enable for the PWRCTRL counter RSTGEN_CLKEN = 0x200 - Clock enable for the RSTGEN SCARD_CLKEN = 0x400 - Clock enable for the SCARD SCARD_ALTAPB_CLKEN = 0x800 - Clock enable for the SCARD ALTAPB STIMER_CNT_CLKEN = 0x1000 - Clock enable for the STIMER_CNT_CLKEN TPIU_CLKEN = 0x2000 - Clock enable for the TPIU_CLKEN UART0HF_CLKEN = 0x4000 - Clock enable for the UART0 HF UART1HF_CLKEN = 0x8000 - Clock enable for the UART1 HF WDT_CLKEN = 0x8000 - Clock enable for the Watchdog timer XT_32KHZ_EN = 0x40000000 - Clock enable for the XT 32KHZ FORCEHFRC = 0x80000000 - HFRC is forced on Status.

### CLOCKEN3STAT - Clock Enable Status

### Address:

Instance 0 Address: | 0x40004030

### Description:

This is a continuation of the clock enable status.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
CLOCKEN3STAT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | CLOCKEN3STAT | RO | Clock enable status 3 DAP_enabled = 0x20000 - DAP clock is enabled [17] VCOMP_enabled = 0x40000 - VCOMP powerdown indicator [18] XTAL_enabled = 0x1000000 - XTAL is enabled [24] HFRC_enabled = 0x2000000 - HFRC is enabled [25] HFADJEN = 0x4000000 - HFRC Adjust enabled [26] HFRC_en_out = 0x8000000 - HFRC Enabled out [27] RTC_XT = 0x10000000 - RTC use XT [28] clkout_xtal_en = 0x20000000 - XTAL clkout enabled [29] clkout_hfrc_en = 0x40000000 - HFRC clkout enabled [30] flashclk_en = 0x80000000 - Flash clk is enabled [31]

### FREQCTRL - HFRC Frequency Control register

### Address:

Instance 0 Address: | 0x40004034

### Description:

This register provides the burst control and burst status.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | BURSTSTATUS 0x0 | BURSTACK 0x0 | BURSTREQ 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED
2 | BURSTSTATUS | RO | This represents frequency burst status.
1 | BURSTACK | RO | Frequency Burst Request Acknowledge. Frequency burst requested is always acknowledged whether burst is granted or not depending on feature enable.
0 | BURSTREQ | RW | Frequency Burst Enable Request DIS = 0x0 - Frequency for ARM core stays at 48MHz EN = 0x1 - Frequency for ARM core is increased to 96MHz

### BLEBUCKTONADJ - BLE BUCK TON ADJUST

### Address:

Instance 0 Address: | 0x4000403C

### Description:

This is the register control for BLE ton adjustment logic.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ZEROLENDETECTEN 0x0 | ZEROLENDETECTTRIM 0x0 | TONADJUSTEN 0x0 | TONADJUSTPERIOD 0x0 | TONHIGHTHRESHOLD 0x0 | TONLOWTHRESHOLD 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:28 | RSVD | RO | RESERVED
27 | ZEROLENDETECTEN | RW | BLEBUCK ZERO LENGTH DETECT ENABLE DIS = 0x0 - Disable Zero Length Detect EN = 0x1 - Enable Zero Length Detect
26:23 | ZEROLENDETECTTRIM | RW | BLEBUCK ZERO LENGTH DETECT TRIM SetF = 0xF - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 81us (10 percent margin of error) or more SetE = 0xE - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 75.6us (10 percent margin of error) or more SetD = 0xD - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 70.2us (10 percent margin of error) or more SetC = 0xC - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 64.8us (10 percent margin of error) or more SetB = 0xB - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 59.4us (10 percent margin of error) or more SetA = 0xA - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 54.0us (10 percent margin of error) or more Set9 = 0x9 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 48.6us (10 percent margin of error) or more Set8 = 0x8 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 43.2us (10 percent margin of error) or more Set7 = 0x7 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 37.8us (10 percent margin of error) or more Set6 = 0x6 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 32.4us (10 percent margin of error) or more Set5 = 0x5 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 27.0us (10 percent margin of error) or more Set4 = 0x4 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 21.6us (10 percent margin of error) or more Set3 = 0x3 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 16.2us (10 percent margin of error) or more Set2 = 0x2 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 10.8us (10 percent margin of error) or more Set1 = 0x1 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 5.4us (10 percent margin of error) or more Set0 = 0x0 - Indicator send when the BLE BUCK asserts blebuck_comp1 for about 2.0us (10 percent margin of error) or more
22 | TONADJUSTEN | RW | TON ADJUST ENABLE DIS = 0x0 - Disable Adjust for BLE BUCK TON trim EN = 0x1 - Enable Adjust for BLE BUCK TON trim
21:20 | TONADJUSTPERIOD | RW | TON ADJUST PERIOD HFRC_3KHz = 0x3 - Adjust done for every 1 3KHz period HFRC_12KHz = 0x2 - Adjust done for every 1 12KHz period HFRC_47KHz = 0x1 - Adjust done for every 1 47KHz period HFRC_94KHz = 0x0 - Adjust done for every 1 94KHz period
19:10 | TONHIGHTHRESHOLD | RW | TON ADJUST HIGH THRESHOLD. Suggested values are #15(94KHz) #2A(47Khz) #A6(12Khz) #29A(3Khz)
9:0 | TONLOWTHRESHOLD | RW | TON ADJUST LOW THRESHOLD. Suggested values are #A(94KHz) #15(47KHz) #53(12Khz) #14D(3Khz)

### INTRPTEN - CLKGEN Interrupt Register: Enable

### Address:

Instance 0 Address: | 0x40004100

### Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OF 0x0 | ACC 0x0 | ACF 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED
2 | OF | RW | XT Oscillator Fail interrupt
1 | ACC | RW | Autocalibration Complete interrupt
0 | ACF | RW | Autocalibration Fail interrupt

### INTRPTSTAT - CLKGEN Interrupt Register: Status

### Address:

Instance 0 Address: | 0x40004104

### Description:

Read bits from this register to discover the cause of a recent interrupt.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OF 0x0 | ACC 0x0 | ACF 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED
2 | OF | RW | XT Oscillator Fail interrupt
1 | ACC | RW | Autocalibration Complete interrupt
0 | ACF | RW | Autocalibration Fail interrupt

### INTRPTCLR - CLKGEN Interrupt Register: Clear

### Address:

Instance 0 Address: | 0x40004108

### Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OF 0x0 | ACC 0x0 | ACF 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED
2 | OF | RW | XT Oscillator Fail interrupt
1 | ACC | RW | Autocalibration Complete interrupt
0 | ACF | RW | Autocalibration Fail interrupt

### INTRPTSET - CLKGEN Interrupt Register: Set

### Address:

Instance 0 Address: | 0x4000410C

### Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OF 0x0 | ACC 0x0 | ACF 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED
2 | OF | RW | XT Oscillator Fail interrupt
1 | ACC | RW | Autocalibration Complete interrupt
0 | ACF | RW | Autocalibration Fail interrupt