| Apollo Register Documentation v2.2.0

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UART - Serial UART

### UART Register Index

0x00000000: | DR - UART Data Register
0x00000004: | RSR - UART Status Register
0x00000018: | FR - Flag Register
0x00000020: | ILPR - IrDA Counter
0x00000024: | IBRD - Integer Baud Rate Divisor
0x00000028: | FBRD - Fractional Baud Rate Divisor
0x0000002C: | LCRH - Line Control High
0x00000030: | CR - Control Register
0x00000034: | IFLS - FIFO Interrupt Level Select
0x00000038: | IER - Interrupt Enable
0x0000003C: | IES - Interrupt Status
0x00000040: | MIS - Masked Interrupt Status
0x00000044: | IEC - Interrupt Clear

### DR - UART Data Register

### Address:

Instance 0 Address: | 0x4001C000
Instance 1 Address: | 0x4001D000
Instance 2 Address: | 0x4001E000

### Description:

UART Data Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OEDATA 0x0 | BEDATA 0x0 | PEDATA 0x0 | FEDATA 0x0 | DATA 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:12 | RSVD | RO | This bitfield is reserved for future use.
11 | OEDATA | RO | This is the overrun error indicator. NOERR = 0x0 - No error on UART OEDATA, overrun error indicator. ERR = 0x1 - Error on UART OEDATA, overrun error indicator.
10 | BEDATA | RO | This is the break error indicator. NOERR = 0x0 - No error on UART BEDATA, break error indicator. ERR = 0x1 - Error on UART BEDATA, break error indicator.
9 | PEDATA | RO | This is the parity error indicator. NOERR = 0x0 - No error on UART PEDATA, parity error indicator. ERR = 0x1 - Error on UART PEDATA, parity error indicator.
8 | FEDATA | RO | This is the framing error indicator. NOERR = 0x0 - No error on UART FEDATA, framing error indicator. ERR = 0x1 - Error on UART FEDATA, framing error indicator.
7:0 | DATA | RW | This is the UART data port.

### RSR - UART Status Register

### Address:

Instance 0 Address: | 0x4001C004
Instance 1 Address: | 0x4001D004
Instance 2 Address: | 0x4001E004

### Description:

UART Status Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OESTAT 0x0 | BESTAT 0x0 | PESTAT 0x0 | FESTAT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:4 | RSVD | RO | This bitfield is reserved for future use.
3 | OESTAT | RW | This is the overrun error indicator. NOERR = 0x0 - No error on UART OESTAT, overrun error indicator. ERR = 0x1 - Error on UART OESTAT, overrun error indicator.
2 | BESTAT | RW | This is the break error indicator. NOERR = 0x0 - No error on UART BESTAT, break error indicator. ERR = 0x1 - Error on UART BESTAT, break error indicator.
1 | PESTAT | RW | This is the parity error indicator. NOERR = 0x0 - No error on UART PESTAT, parity error indicator. ERR = 0x1 - Error on UART PESTAT, parity error indicator.
0 | FESTAT | RW | This is the framing error indicator. NOERR = 0x0 - No error on UART FESTAT, framing error indicator. ERR = 0x1 - Error on UART FESTAT, framing error indicator.

### FR - Flag Register

### Address:

Instance 0 Address: | 0x4001C018
Instance 1 Address: | 0x4001D018
Instance 2 Address: | 0x4001E018

### Description:

Flag Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | TXBUSY 0x0 | TXFE 0x0 | RXFF 0x0 | TXFF 0x0 | RXFE 0x0 | BUSY 0x0 | DCD 0x0 | DSR 0x0 | CTS 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:9 | RSVD | RO | This bitfield is reserved for future use.
8 | TXBUSY | RO | This bit holds the transmit BUSY indicator.
7 | TXFE | RO | This bit holds the transmit FIFO empty indicator. XMTFIFO_EMPTY = 0x1 - Transmit fifo is empty.
6 | RXFF | RO | This bit holds the receive FIFO full indicator. RCVFIFO_FULL = 0x1 - Receive fifo is full.
5 | TXFF | RO | This bit holds the transmit FIFO full indicator. XMTFIFO_FULL = 0x1 - Transmit fifo is full.
4 | RXFE | RO | This bit holds the receive FIFO empty indicator. RCVFIFO_EMPTY = 0x1 - Receive fifo is empty.
3 | BUSY | RO | This bit holds the busy indicator. BUSY = 0x1 - UART busy indicator.
2 | DCD | RO | This bit holds the data carrier detect indicator. DETECTED = 0x1 - Data carrier detect detected.
1 | DSR | RO | This bit holds the data set ready indicator. READY = 0x1 - Data set ready.
0 | CTS | RO | This bit holds the clear to send indicator. CLEARTOSEND = 0x1 - Clear to send is indicated.

### ILPR - IrDA Counter

### Address:

Instance 0 Address: | 0x4001C020
Instance 1 Address: | 0x4001D020
Instance 2 Address: | 0x4001E020

### Description:

IrDA Counter

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | ILPDVSR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:8 | RSVD | RO | This bitfield is reserved for future use.
7:0 | ILPDVSR | RW | These bits hold the IrDA counter divisor.

### IBRD - Integer Baud Rate Divisor

### Address:

Instance 0 Address: | 0x4001C024
Instance 1 Address: | 0x4001D024
Instance 2 Address: | 0x4001E024

### Description:

Integer Baud Rate Divisor

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DIVINT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | RSVD | RO | This bitfield is reserved for future use.
15:0 | DIVINT | RW | These bits hold the baud integer divisor.

### FBRD - Fractional Baud Rate Divisor

### Address:

Instance 0 Address: | 0x4001C028
Instance 1 Address: | 0x4001D028
Instance 2 Address: | 0x4001E028

### Description:

Fractional Baud Rate Divisor

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DIVFRAC 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:6 | RSVD | RO | This bitfield is reserved for future use.
5:0 | DIVFRAC | RW | These bits hold the baud fractional divisor.

### LCRH - Line Control High

### Address:

Instance 0 Address: | 0x4001C02C
Instance 1 Address: | 0x4001D02C
Instance 2 Address: | 0x4001E02C

### Description:

Line Control High

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | SPS 0x0 | WLEN 0x0 | FEN 0x0 | STP2 0x0 | EPS 0x0 | PEN 0x0 | BRK 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:8 | RSVD | RO | This bitfield is reserved for future use.
7 | SPS | RW | This bit holds the stick parity select.
6:5 | WLEN | RW | These bits hold the write length.
4 | FEN | RW | This bit holds the FIFO enable.
3 | STP2 | RW | This bit holds the two stop bits select.
2 | EPS | RW | This bit holds the even parity select.
1 | PEN | RW | This bit holds the parity enable.
0 | BRK | RW | This bit holds the break set.

### CR - Control Register

### Address:

Instance 0 Address: | 0x4001C030
Instance 1 Address: | 0x4001D030
Instance 2 Address: | 0x4001E030

### Description:

Control Register

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | CTSEN 0x0 | RTSEN 0x0 | OUT2 0x0 | OUT1 0x0 | RTS 0x0 | DTR 0x0 | RXE 0x1 | TXE 0x1 | LBE 0x0 | CLKSEL 0x0 | CLKEN 0x0 | SIRLP 0x0 | SIREN 0x0 | UARTEN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:16 | RSVD | RO | This bitfield is reserved for future use.
15 | CTSEN | RW | This bit enables CTS hardware flow control.
14 | RTSEN | RW | This bit enables RTS hardware flow control.
13 | OUT2 | RW | This bit holds modem Out2.
12 | OUT1 | RW | This bit holds modem Out1.
11 | RTS | RW | This bit enables request to send.
10 | DTR | RW | This bit enables data transmit ready.
9 | RXE | RW | This bit is the receive enable.
8 | TXE | RW | This bit is the transmit enable.
7 | LBE | RW | This bit is the loopback enable.
6:4 | CLKSEL | RW | This bitfield is the UART clock select. NOCLK = 0x0 - No UART clock. This is the low power default. 24MHZ = 0x1 - 24 MHz clock. Must be used if CLKGEN CORESEL=0. 12MHZ = 0x2 - 12 MHz clock. Must be used if CLKGEN CORESEL=1. Note that CORESEL=1 is unsupported by the IO Master. 6MHZ = 0x3 - 6 MHz clock. Must be used if CLKGEN CORESEL=2, 3, or 4. Note that CORESEL=2 is unsupported. 3MHZ = 0x4 - 3 MHz clock. Must be used if CLKGEN CORESEL=5, 6, or 7. RSVD5 = 0x5 - Reserved. RSVD6 = 0x6 - Reserved. RSVD7 = 0x7 - Reserved.
3 | CLKEN | RW | This bit is the UART clock enable.
2 | SIRLP | RW | This bit is the SIR low power select.
1 | SIREN | RW | This bit is the SIR ENDEC enable.
0 | UARTEN | RW | This bit is the UART enable.

### IFLS - FIFO Interrupt Level Select

### Address:

Instance 0 Address: | 0x4001C034
Instance 1 Address: | 0x4001D034
Instance 2 Address: | 0x4001E034

### Description:

FIFO Interrupt Level Select

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | RXIFLSEL 0x2 | TXIFLSEL 0x2

Bits | Name | RW | Description
--- | --- | --- | ---
31:6 | RSVD | RO | This bitfield is reserved for future use.
5:3 | RXIFLSEL | RW | These bits hold the receive FIFO interrupt level.
2:0 | TXIFLSEL | RW | These bits hold the transmit FIFO interrupt level.

### IER - Interrupt Enable

### Address:

Instance 0 Address: | 0x4001C038
Instance 1 Address: | 0x4001D038
Instance 2 Address: | 0x4001E038

### Description:

Interrupt Enable

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OEIM 0x0 | BEIM 0x0 | PEIM 0x0 | FEIM 0x0 | RTIM 0x0 | TXIM 0x0 | RXIM 0x0 | DSRMIM 0x0 | DCDMIM 0x0 | CTSMIM 0x0 | TXCMPMIM 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | This bitfield is reserved for future use.
10 | OEIM | RW | This bit holds the overflow interrupt enable.
9 | BEIM | RW | This bit holds the break error interrupt enable.
8 | PEIM | RW | This bit holds the parity error interrupt enable.
7 | FEIM | RW | This bit holds the framing error interrupt enable.
6 | RTIM | RW | This bit holds the receive timeout interrupt enable.
5 | TXIM | RW | This bit holds the transmit interrupt enable.
4 | RXIM | RW | This bit holds the receive interrupt enable.
3 | DSRMIM | RW | This bit holds the modem DSR interrupt enable.
2 | DCDMIM | RW | This bit holds the modem DCD interrupt enable.
1 | CTSMIM | RW | This bit holds the modem CTS interrupt enable.
0 | TXCMPMIM | RW | This bit holds the modem TXCMP interrupt enable.

### IES - Interrupt Status

### Address:

Instance 0 Address: | 0x4001C03C
Instance 1 Address: | 0x4001D03C
Instance 2 Address: | 0x4001E03C

### Description:

Interrupt Status

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OERIS 0x0 | BERIS 0x0 | PERIS 0x0 | FERIS 0x0 | RTRIS 0x0 | TXRIS 0x0 | RXRIS 0x0 | DSRMRIS 0x0 | DCDMRIS 0x0 | CTSMRIS 0x0 | TXCMPMRIS 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | This bitfield is reserved for future use.
10 | OERIS | RO | This bit holds the overflow interrupt status.
9 | BERIS | RO | This bit holds the break error interrupt status.
8 | PERIS | RO | This bit holds the parity error interrupt status.
7 | FERIS | RO | This bit holds the framing error interrupt status.
6 | RTRIS | RO | This bit holds the receive timeout interrupt status.
5 | TXRIS | RO | This bit holds the transmit interrupt status.
4 | RXRIS | RO | This bit holds the receive interrupt status.
3 | DSRMRIS | RO | This bit holds the modem DSR interrupt status.
2 | DCDMRIS | RO | This bit holds the modem DCD interrupt status.
1 | CTSMRIS | RO | This bit holds the modem CTS interrupt status.
0 | TXCMPMRIS | RO | This bit holds the modem TXCMP interrupt status.

### MIS - Masked Interrupt Status

### Address:

Instance 0 Address: | 0x4001C040
Instance 1 Address: | 0x4001D040
Instance 2 Address: | 0x4001E040

### Description:

Masked Interrupt Status

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OEMIS 0x0 | BEMIS 0x0 | PEMIS 0x0 | FEMIS 0x0 | RTMIS 0x0 | TXMIS 0x0 | RXMIS 0x0 | DSRMMIS 0x0 | DCDMMIS 0x0 | CTSMMIS 0x0 | TXCMPMMIS 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | This bitfield is reserved for future use.
10 | OEMIS | RO | This bit holds the overflow interrupt status masked.
9 | BEMIS | RO | This bit holds the break error interrupt status masked.
8 | PEMIS | RO | This bit holds the parity error interrupt status masked.
7 | FEMIS | RO | This bit holds the framing error interrupt status masked.
6 | RTMIS | RO | This bit holds the receive timeout interrupt status masked.
5 | TXMIS | RO | This bit holds the transmit interrupt status masked.
4 | RXMIS | RO | This bit holds the receive interrupt status masked.
3 | DSRMMIS | RO | This bit holds the modem DSR interrupt status masked.
2 | DCDMMIS | RO | This bit holds the modem DCD interrupt status masked.
1 | CTSMMIS | RO | This bit holds the modem CTS interrupt status masked.
0 | TXCMPMMIS | RO | This bit holds the modem TXCMP interrupt status masked.

### IEC - Interrupt Clear

### Address:

Instance 0 Address: | 0x4001C044
Instance 1 Address: | 0x4001D044
Instance 2 Address: | 0x4001E044

### Description:

Interrupt Clear

### Example Macro Usage:

    //
    // All macro-based register writes follow the same basic format. For
    // single-instance modules, you may use the simpler AM_REG macro. For
    // multi-instance macros, you will need to specify the instance number using
    // the AM_REGn macro format.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    // AM_REGn(<MODULE>, <INSTANCE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>_<VALUE>;
    //
    // For registers that do not have specific enumeration values, you may use this alternate format instead.
    //
    // AM_REG(<MODULE>, <REGISTER>) |= AM_REG_<MODULE>_<REGISTER>_<FIELD>(<NUMBER>);
    //
    // For example, the following three lines of code are equivalent methods of
    // writing the value for 12MHZ to the CLKSEL field in the ADC_CFG register.
    //
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REGn(ADC, 0, CFG) |= AM_REG_ADC_CFG_CLKSEL_12MHZ;
    AM_REG(ADC, CFG) |= AM_REG_ADC_CFG_CLKSEL(0x1);

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | OEIC 0x0 | BEIC 0x0 | PEIC 0x0 | FEIC 0x0 | RTIC 0x0 | TXIC 0x0 | RXIC 0x0 | DSRMIC 0x0 | DCDMIC 0x0 | CTSMIC 0x0 | TXCMPMIC 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | This bitfield is reserved for future use.
10 | OEIC | WO | This bit holds the overflow interrupt clear.
9 | BEIC | WO | This bit holds the break error interrupt clear.
8 | PEIC | WO | This bit holds the parity error interrupt clear.
7 | FEIC | WO | This bit holds the framing error interrupt clear.
6 | RTIC | WO | This bit holds the receive timeout interrupt clear.
5 | TXIC | WO | This bit holds the transmit interrupt clear.
4 | RXIC | WO | This bit holds the receive interrupt clear.
3 | DSRMIC | WO | This bit holds the modem DSR interrupt clear.
2 | DCDMIC | WO | This bit holds the modem DCD interrupt clear.
1 | CTSMIC | WO | This bit holds the modem CTS interrupt clear.
0 | TXCMPMIC | WO | This bit holds the modem TXCMP interrupt clear.