| Apollo Register Documentation v2.2.0

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PDM - PDM Audio

### PDM Register Index

0x00000000: | PCFG - PDM Configuration Register
0x00000004: | VCFG - Voice Configuration Register
0x00000008: | VOICESTAT - Voice Status Register
0x0000000C: | FIFOREAD - FIFO Read
0x00000010: | FIFOFLUSH - FIFO Flush
0x00000014: | FIFOTHR - FIFO Threshold
0x00000200: | INTEN - IO Master Interrupts: Enable
0x00000204: | INTSTAT - IO Master Interrupts: Status
0x00000208: | INTCLR - IO Master Interrupts: Clear
0x0000020C: | INTSET - IO Master Interrupts: Set
0x00000240: | DMATRIGEN - DMA Trigger Enable Register
0x00000244: | DMATRIGSTAT - DMA Trigger Status Register
0x00000280: | DMACFG - DMA Configuration Register
0x00000288: | DMATOTCOUNT - DMA Total Transfer Count
0x0000028C: | DMATARGADDR - DMA Target Address Register
0x00000290: | DMASTAT - DMA Status Register

### PCFG - PDM Configuration Register

### Address:

Instance 0 Address: | 0x50011000

### Description:

PDM Configuration Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
LRSWAP 0x0 | PGARIGHT 0x0 | PGALEFT 0x0 | RSVD 0x0 | MCLKDIV 0x0 | SINCRATE 0x30 | ADCHPD 0x1 | HPCUTOFF 0xb | CYCLES 0x1 | SOFTMUTE 0x0 | PDMCOREEN 0x1

Bits | Name | RW | Description
--- | --- | --- | ---
31 | LRSWAP | RW | Left/right channel swap. EN = 0x1 - Swap left and right channels (FIFO Read RIGHT_LEFT). NOSWAP = 0x0 - No channel swapping (IFO Read LEFT_RIGHT).
30:26 | PGARIGHT | RW | Right channel PGA gain. P405DB = 0x1F - 40.5 db gain. P390DB = 0x1E - 39.0 db gain. P375DB = 0x1D - 37.5 db gain. P360DB = 0x1C - 36.0 db gain. P345DB = 0x1B - 34.5 db gain. P330DB = 0x1A - 33.0 db gain. P315DB = 0x19 - 31.5 db gain. P300DB = 0x18 - 30.0 db gain. P285DB = 0x17 - 28.5 db gain. P270DB = 0x16 - 27.0 db gain. P255DB = 0x15 - 25.5 db gain. P240DB = 0x14 - 24.0 db gain. P225DB = 0x13 - 22.5 db gain. P210DB = 0x12 - 21.0 db gain. P195DB = 0x11 - 19.5 db gain. P180DB = 0x10 - 18.0 db gain. P165DB = 0xF - 16.5 db gain. P150DB = 0xE - 15.0 db gain. P135DB = 0xD - 13.5 db gain. P120DB = 0xC - 12.0 db gain. P105DB = 0xB - 10.5 db gain. P90DB = 0xA - 9.0 db gain. P75DB = 0x9 - 7.5 db gain. P60DB = 0x8 - 6.0 db gain. P45DB = 0x7 - 4.5 db gain. P30DB = 0x6 - 3.0 db gain. P15DB = 0x5 - 1.5 db gain. 0DB = 0x4 - 0.0 db gain. M15DB = 0x3 - -1.5 db gain. M300DB = 0x2 - -3.0 db gain. M45DB = 0x1 - -4.5 db gain. M60DB = 0x0 - -6.0 db gain.
25:21 | PGALEFT | RW | Left channel PGA gain. P405DB = 0x1F - 40.5 db gain. P390DB = 0x1E - 39.0 db gain. P375DB = 0x1D - 37.5 db gain. P360DB = 0x1C - 36.0 db gain. P345DB = 0x1B - 34.5 db gain. P330DB = 0x1A - 33.0 db gain. P315DB = 0x19 - 31.5 db gain. P300DB = 0x18 - 30.0 db gain. P285DB = 0x17 - 28.5 db gain. P270DB = 0x16 - 27.0 db gain. P255DB = 0x15 - 25.5 db gain. P240DB = 0x14 - 24.0 db gain. P225DB = 0x13 - 22.5 db gain. P210DB = 0x12 - 21.0 db gain. P195DB = 0x11 - 19.5 db gain. P180DB = 0x10 - 18.0 db gain. P165DB = 0xF - 16.5 db gain. P150DB = 0xE - 15.0 db gain. P135DB = 0xD - 13.5 db gain. P120DB = 0xC - 12.0 db gain. P105DB = 0xB - 10.5 db gain. P90DB = 0xA - 9.0 db gain. P75DB = 0x9 - 7.5 db gain. P60DB = 0x8 - 6.0 db gain. P45DB = 0x7 - 4.5 db gain. P30DB = 0x6 - 3.0 db gain. P15DB = 0x5 - 1.5 db gain. 0DB = 0x4 - 0.0 db gain. M15DB = 0x3 - -1.5 db gain. M300DB = 0x2 - -3.0 db gain. M45DB = 0x1 - -4.5 db gain. M60DB = 0x0 - -6.0 db gain.
20:19 | RSVD | RO | This bitfield is reserved for future use.
18:17 | MCLKDIV | RW | PDM_CLK frequency divisor. MCKDIV4 = 0x3 - Divide input clock by 4 MCKDIV3 = 0x2 - Divide input clock by 3 MCKDIV2 = 0x1 - Divide input clock by 2 MCKDIV1 = 0x0 - Divide input clock by 1
16:10 | SINCRATE | RW | SINC decimation rate.
9 | ADCHPD | RW | High pass filter control. EN = 0x1 - Enable high pass filter. DIS = 0x0 - Disable high pass filter.
8:5 | HPCUTOFF | RW | High pass filter coefficients.
4:2 | CYCLES | RW | Number of clocks during gain-setting changes.
1 | SOFTMUTE | RW | Soft mute control. EN = 0x1 - Enable Soft Mute. DIS = 0x0 - Disable Soft Mute.
0 | PDMCOREEN | RW | Data Streaming Control. EN = 0x1 - Enable Data Streaming. DIS = 0x0 - Disable Data Streaming.

### VCFG - Voice Configuration Register

### Address:

Instance 0 Address: | 0x50011004

### Description:

Voice Configuration Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
IOCLKEN 0x0 | RSTB 0x0 | PDMCLKSEL 0x0 | PDMCLKEN 0x0 | RSVD 0x0 | I2SEN 0x0 | BCLKINV 0x0 | RSVD 0x0 | DMICKDEL 0x0 | SELAP 0x0 | RSVD 0x0 | PCMPACK 0x0 | RSVD 0x0 | CHSET 0x1 | RSVD 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31 | IOCLKEN | RW | Enable the IO clock. DIS = 0x0 - Disable FIFO read. EN = 0x1 - Enable FIFO read.
30 | RSTB | RW | Reset the IP core. RESET = 0x0 - Reset the core. NORM = 0x1 - Enable the core.
29:27 | PDMCLKSEL | RW | Select the PDM input clock. DISABLE = 0x0 - Static value. 12MHz = 0x1 - PDM clock is 12 MHz. 6MHz = 0x2 - PDM clock is 6 MHz. 3MHz = 0x3 - PDM clock is 3 MHz. 1_5MHz = 0x4 - PDM clock is 1.5 MHz. 750KHz = 0x5 - PDM clock is 750 KHz. 375KHz = 0x6 - PDM clock is 375 KHz. 187KHz = 0x7 - PDM clock is 187.5 KHz.
26 | PDMCLKEN | RW | Enable the serial clock. DIS = 0x0 - Disable serial clock. EN = 0x1 - Enable serial clock.
25:21 | RSVD | RO | This bitfield is reserved for future use.
20 | I2SEN | RW | I2S interface enable. DIS = 0x0 - Disable I2S interface. EN = 0x1 - Enable I2S interface.
19 | BCLKINV | RW | I2S BCLK input inversion. INV = 0x0 - BCLK inverted. NORM = 0x1 - BCLK not inverted.
18 | RSVD | RO | This bitfield is reserved for future use.
17 | DMICKDEL | RW | PDM clock sampling delay. 0CYC = 0x0 - No delay. 1CYC = 0x1 - 1 cycle delay.
16 | SELAP | RW | Select PDM input clock source. I2S = 0x1 - Clock source from I2S BCLK. INTERNAL = 0x0 - Clock source from internal clock generator.
15:9 | RSVD | RO | This bitfield is reserved for future use.
8 | PCMPACK | RW | PCM data packing enable. DIS = 0x0 - Disable PCM packing. EN = 0x1 - Enable PCM packing.
7:5 | RSVD | RO | This bitfield is reserved for future use.
4:3 | CHSET | RW | Set PCM channels. DIS = 0x0 - Channel disabled. LEFT = 0x1 - Mono left channel. RIGHT = 0x2 - Mono right channel. STEREO = 0x3 - Stereo channels.
2:0 | RSVD | RO | This bitfield is reserved for future use.

### VOICESTAT - Voice Status Register

### Address:

Instance 0 Address: | 0x50011008

### Description:

Voice Status Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | FIFOCNT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:6 | RSVD | RO | This bitfield is reserved for future use.
5:0 | FIFOCNT | RO | Valid 32-bit entries currently in the FIFO.

### FIFOREAD - FIFO Read

### Address:

Instance 0 Address: | 0x5001100C

### Description:

FIFO Read

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
FIFOREAD 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:0 | FIFOREAD | RO | FIFO read data.

### FIFOFLUSH - FIFO Flush

### Address:

Instance 0 Address: | 0x50011010

### Description:

FIFO Flush

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | FIFOFLUSH 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:1 | RSVD | RO | This bitfield is reserved for future use.
0 | FIFOFLUSH | WO | FIFO FLUSH.

### FIFOTHR - FIFO Threshold

### Address:

Instance 0 Address: | 0x50011014

### Description:

FIFO Threshold

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | FIFOTHR 0x10

Bits | Name | RW | Description
--- | --- | --- | ---
31:5 | RSVD | RO | This bitfield is reserved for future use.
4:0 | FIFOTHR | RW | FIFO Threshold value. When the FIFO count is equal to, or larger than this value (in words), a THR interrupt is generated (if enabled)

### INTEN - IO Master Interrupts: Enable

### Address:

Instance 0 Address: | 0x50011200

### Description:

Set bits in this register to allow this module to generate the corresponding interrupt.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DERR 0x0 | DCMP 0x0 | UNDFL 0x0 | OVF 0x0 | THR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:5 | RSVD | RO | RESERVED
4 | DERR | RW | DMA Error receieved
3 | DCMP | RW | DMA completed a transfer
2 | UNDFL | RW | This is the FIFO underflow interrupt.
1 | OVF | RW | This is the FIFO overflow interrupt.
0 | THR | RW | This is the FIFO threshold interrupt.

### INTSTAT - IO Master Interrupts: Status

### Address:

Instance 0 Address: | 0x50011204

### Description:

Read bits from this register to discover the cause of a recent interrupt.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DERR 0x0 | DCMP 0x0 | UNDFL 0x0 | OVF 0x0 | THR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:5 | RSVD | RO | RESERVED
4 | DERR | RW | DMA Error receieved
3 | DCMP | RW | DMA completed a transfer
2 | UNDFL | RW | This is the FIFO underflow interrupt.
1 | OVF | RW | This is the FIFO overflow interrupt.
0 | THR | RW | This is the FIFO threshold interrupt.

### INTCLR - IO Master Interrupts: Clear

### Address:

Instance 0 Address: | 0x50011208

### Description:

Write a 1 to a bit in this register to clear the interrupt status associated with that bit.

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DERR 0x0 | DCMP 0x0 | UNDFL 0x0 | OVF 0x0 | THR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:5 | RSVD | RO | RESERVED
4 | DERR | RW | DMA Error receieved
3 | DCMP | RW | DMA completed a transfer
2 | UNDFL | RW | This is the FIFO underflow interrupt.
1 | OVF | RW | This is the FIFO overflow interrupt.
0 | THR | RW | This is the FIFO threshold interrupt.

### INTSET - IO Master Interrupts: Set

### Address:

Instance 0 Address: | 0x5001120C

### Description:

Write a 1 to a bit in this register to instantly generate an interrupt from this module. (Generally used for testing purposes).

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DERR 0x0 | DCMP 0x0 | UNDFL 0x0 | OVF 0x0 | THR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:5 | RSVD | RO | RESERVED
4 | DERR | RW | DMA Error receieved
3 | DCMP | RW | DMA completed a transfer
2 | UNDFL | RW | This is the FIFO underflow interrupt.
1 | OVF | RW | This is the FIFO overflow interrupt.
0 | THR | RW | This is the FIFO threshold interrupt.

### DMATRIGEN - DMA Trigger Enable Register

### Address:

Instance 0 Address: | 0x50011240

### Description:

DMA Trigger Enable Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DTHR90 0x0 | DTHR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:2 | RSVD | RO | RESERVED.
1 | DTHR90 | RW | Trigger DMA at FIFO 90 percent full. This signal is also used internally for AUTOHIP function
0 | DTHR | RW | Trigger DMA upon when FIFO iss filled to level indicated by the FIFO THRESHOLD,at granularity of 16 bytes only

### DMATRIGSTAT - DMA Trigger Status Register

### Address:

Instance 0 Address: | 0x50011244

### Description:

DMA Trigger Status Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DTHR90STAT 0x0 | DTHRSTAT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:2 | RSVD | RO | RESERVED.
1 | DTHR90STAT | RO | Triggered DMA from FIFO reaching 90 percent full
0 | DTHRSTAT | RO | Triggered DMA from FIFO reaching threshold

### DMACFG - DMA Configuration Register

### Address:

Instance 0 Address: | 0x50011280

### Description:

DMA Configuration Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DPWROFF 0x0 | DAUTOHIP 0x0 | DMAPRI 0x0 | RSVD 0x0 | DMADIR 0x0 | RSVD 0x0 | DMAEN 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:11 | RSVD | RO | RESERVED.
10 | DPWROFF | RW | Power Off the ADC System upon DMACPL.
9 | DAUTOHIP | RW | Raise priority to high on fifo full, and DMAPRI set to low
8 | DMAPRI | RW | Sets the Priority of the DMA request LOW = 0x0 - Low Priority (service as best effort) HIGH = 0x1 - High Priority (service immediately)
7:3 | RSVD | RO | RESERVED.
2 | DMADIR | RO | Direction P2M = 0x0 - Peripheral to Memory (SRAM) transaction. THe PDM module will only DMA to memory. M2P = 0x1 - Memory to Peripheral transaction. Not available for PDM module
1 | RSVD | RO | RESERVED.
0 | DMAEN | RW | DMA Enable DIS = 0x0 - Disable DMA Function EN = 0x1 - Enable DMA Function

### DMATOTCOUNT - DMA Total Transfer Count

### Address:

Instance 0 Address: | 0x50011288

### Description:

DMA Total Transfer Count

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | TOTCOUNT 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:20 | RSVD | RO | RESERVED.
19:0 | TOTCOUNT | RW | Total Transfer Count. The transfer count must be a multiple of the THR setting to avoid DMA overruns.

### DMATARGADDR - DMA Target Address Register

### Address:

Instance 0 Address: | 0x5001128C

### Description:

DMA Target Address Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
UTARGADDR 0x100 | LTARGADDR 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:20 | UTARGADDR | RO | SRAM Target
19:0 | LTARGADDR | RW | DMA Target Address. This register is not updated with the current address of the DMA, but will remain static with the original address during the DMA transfer.

### DMASTAT - DMA Status Register

### Address:

Instance 0 Address: | 0x50011290

### Description:

DMA Status Register

### Example Macro Usage:

    //
    // Register access is all performed through the standard CMSIS structure-based
    // interface. This includes module-level structure definitions with members and
    // bitfields corresponding to the physical registers and bitfields within each
    // module. In addition, Ambiq has provided instance-level macros for modules
    // that have more than one physical instance and a generic AM_REGVAL() macro
    // for directly accessing memory by address.
    //
    // The following examples show how to use these structures and macros:

    // Setting the ADC configuration register...
    AM_REGVAL(0x50010000) = 0x1234;              // by address.
    ADC->CFG = 0x1234;                           // by structure pointer.
    ADCn(0)->CFG = 0x1234;                       // by structure pointer (with instance number).

    // Changing the ADC clock...
    ADCn(0)->CFG_b.CLKSEL = 0x2;                 // by raw value.
    ADCn(0)->CFG_b.CLKSEL = ADC_CFG_CLKSEL_HFRC; // using an enumerated value.

### Register Fields:

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
--- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | ---
RSVD 0x0 | DMAERR 0x0 | DMACPL 0x0 | DMATIP 0x0

Bits | Name | RW | Description
--- | --- | --- | ---
31:3 | RSVD | RO | RESERVED.
2 | DMAERR | RW | DMA Error
1 | DMACPL | RW | DMA Transfer Complete
0 | DMATIP | RW | DMA Transfer In Progress